Joint design-time and post-silicon optimization for digitally tuned analog circuits

• Published in: 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers pp. 725 - 730
• Main Authors: Wei Yao, Yiyu Shi, Lei He, Pamarti, S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2009
• Subjects: Analog circuits; Capacitance; Circuit optimization; Constraint optimization; Design optimization; Optimization methods; Phase locked loops; Space exploration; Transmitters; Tunable circuits and devices
• ISSN: 1092-3152
• DOI: 10.1145/1687399.1687534

Joint design time and post-silicon optimization for analog circuits has been an open problem in literature because of the complex nature of analog circuit modeling and optimization. In this paper we formulate the co-optimization problem for digitally tuned analog circuits to optimize the parametric yield, subject to power and area constraints. A general optimization framework combing the branch-and-bound algorithm and gradient ascent method is proposed. We demonstrate our framework with two examples in high-speed serial link, the transmitter design and the phase-locked-loop (PLL) design. Simulation results show that compared with the design heuristic from analog designers' perspective, joint design-time and post-silicon optimization can improve the yield by up to 47% for transmitter design and up to 56% for PLL design under the same area and power constraints. To the best of the authors' knowledge, this is the first in-depth study on yield-driven analog circuit design technique that optimizes post-silicon tuning together with the design-time optimization.