A 7.6 mW 1.75 GS/s 5 bit flash A/D converter in 90 nm digital CMOS
Verbruggen, B., Wambacq, P., Kuijk, M., Van der Plas, G.
Published in 2008 IEEE Symposium on VLSI Circuits (01.06.2008)
Published in 2008 IEEE Symposium on VLSI Circuits (01.06.2008)
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Micro-mirror arrays
VAN DER PLAS GEERT, JAYAPALA MURALI, ROCHUS VERONIQUE, SEVERI SIMONE, ROTTENBERG XAVIER
Year of Publication 22.12.2015
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Year of Publication 22.12.2015
Patent
Design issues in heterogeneous 3D/2.5D integration
Milojevic, D., Marchal, P., Marinissen, E. J., Van der Plas, G., Verkest, D., Beyne, E.
Published in 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) (01.01.2013)
Published in 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) (01.01.2013)
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Conference Proceeding
Calibration of micro-mirror arrays
VAN DER PLAS GEERT, DONNAY STÉPHANE, JAYAPALA MURALI, ROCHUS VERONIQUE, SEVERI SIMONE, ROTTENBERG XAVIER
Year of Publication 01.12.2015
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Year of Publication 01.12.2015
Patent
METHOD AND SYSTEM FOR MEASURING CAPACITANCE DIFFERENCE BETWEEN CAPACITIVE ELEMENTS
ANCHLIA, ANKUR, MIYAMORI, YUICHI, MERCHA, ABDELKARIM, SAWADA, KEN, VAN DER PLAS, GEERT
Year of Publication 25.11.2015
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Year of Publication 25.11.2015
Patent
Calibration of micro-mirror arrays
ROCHUS, VERONIQUE, ROTTENBERG, XAVIER, JAYAPALA, MURALI, VAN DER PLAS, GEERT, DONNAY, STEPHANE, SEVERI, SIMONE
Year of Publication 04.11.2015
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Year of Publication 04.11.2015
Patent
A 6-bit 50-MS/s threshold configuring SAR ADC in 90-nm digital CMOS
Nuzzo, Pierluigi, Nani, Claudio, Armiento, Costantino, Sangiovanni-Vincentelli, Alberto, Craninckx, Jan, Van der Plas, Geert
Published in 2009 Symposium on VLSI Circuits (01.06.2009)
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Published in 2009 Symposium on VLSI Circuits (01.06.2009)
Conference Proceeding
Sigma-delta based analog to digital converter
BORREMANS, JONATHAN, VAN DER PLAS, GEERT, BOS, LYNN, RYCKAERT, JULIEN
Year of Publication 28.11.2012
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Year of Publication 28.11.2012
Patent
METHOD AND SYSTEM FOR MEASURING CAPACITANCE DIFFERENCE BETWEEN CAPACITIVE ELEMENTS
SAWADA KEN, MIYAMORI YUICHI, VAN DER PLAS GEERT, MERCHA ABDELKARIM, ANCHLIA ANKUR
Year of Publication 18.12.2014
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Year of Publication 18.12.2014
Patent
Micro-Mirror Arrays
VAN DER PLAS GEERT, JAYAPALA MURALI, ROCHUS VERONIQUE, SEVERI SIMONE, ROTTENBERG XAVIER
Year of Publication 18.12.2014
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Year of Publication 18.12.2014
Patent
IMPROVEMENTS IN OR RELATING TO MICRO-MIRROR ARRAYS
ROCHUS, VERONIQUE, ROTTENBERG, XAVIER, JAYAPALA, MURALI, VAN DER PLAS, GEERT, SEVERI, SIMONE
Year of Publication 26.11.2014
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Year of Publication 26.11.2014
Patent
METHOD AND SYSTEM FOR MEASURING CAPACITANCE DIFFERENCE BETWEEN CAPACITIVE ELEMENTS
ANCHLIA, ANKUR, MIYAMORI, YUICHI, MERCHA, ABDELKARIM, SAWADA, KEN, VAN DER PLAS, GEERT
Year of Publication 29.10.2014
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Year of Publication 29.10.2014
Patent
A METHOD FOR PRODUCING A THROUGH SEMICONDUCTOR VIA CONNECTION
Van der Plas, Mr. Geert, Hiblot, Mr. Gaspard, Van Huylenbroeck, Mr. Stefaan
Year of Publication 18.11.2020
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Year of Publication 18.11.2020
Patent
High temperature calibration of a compact model for GaN-on-Si power switches
Stoffels, Steve, Marcon, Denis, Geens, Karen, Kang, Xuanwu, Van Der Plas, Geert, Van Hove, Marleen, Decoutere, Stefaan
Published in 2011 17th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC) (01.09.2011)
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Published in 2011 17th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC) (01.09.2011)
Conference Proceeding