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Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics
Guilley, Sylvain, Sauvage, Laurent, Flament, Florent, Vinh-Nga Vong, Hoogvorst, Philippe, Pacalet, Renaud
Published in IEEE transactions on computers (01.09.2010)
Published in IEEE transactions on computers (01.09.2010)
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Journal Article