ARUZ — Large-scale, massively parallel FPGA-based analyzer of real complex systems
Kiełbik, Rafał, Hałagan, Krzysztof, Zatorski, Witold, Jung, Jarosław, Ulański, Jacek, Napieralski, Andrzej, Rudnicki, Kamil, Amrozik, Piotr, Jabłoński, Grzegorz, Stożek, Dominik, Polanowski, Piotr, Mudza, Zbigniew, Kupis, Joanna, Panek, Przemysław
Published in Computer physics communications (01.11.2018)
Published in Computer physics communications (01.11.2018)
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Journal Article
A PANEL WITH ELECTRONIC CIRCUITS AND A SET OF PANELS
Napieralski, Andrzej, PAKULA, Tadeusz, Polanowski, Piotr, Jung, Jaroslaw, Kielbik, Rafal, Ulanski, Jacek, Zatorski, Witold, Halagan, Krzysztof
Year of Publication 01.08.2018
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Year of Publication 01.08.2018
Patent
SYSTEM OF ELECTRONIC MODULES HAVING A REDUNDANT CONFIGURATION
NAPIERALSKI, ANDRZEJ, HALAGAN, KRZYSZTOF, PAKUŁA, TADEUSZ, ZATORSKI, WITOLD, ULAŃSKI, JACEK, KIEŁBIK, RAFAŁ, JUNG, JAROSŁAW, POLANOWSKI, PIOTR
Year of Publication 31.01.2018
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Year of Publication 31.01.2018
Patent
SYSTEM OF ELECTRONIC MODULES HAVING A REDUNDANT CONFIGURATION
Napieralski, Andrzej, Pakula, Tadeusz, Polanowski, Piotr, Jung, Jaroslaw, Kielbik, Rafal, Ulanski, Jacek, Zatorski, Witold, Halagan, Krzysztof
Year of Publication 23.08.2017
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Year of Publication 23.08.2017
Patent
A PANEL WITH ELECTRONIC CIRCUITS AND A SET OF PANELS
KIELBIK, RAFAL, NAPIERALSKI, ANDRZEJ, HALAGAN, KRZYSZTOF, ZATORSKI, WITOLD, ULANSKI, JACEK, PAKULA, TADEUSZ, JUNG, JAROSLAW, POLANOWSKI, PIOTR
Year of Publication 12.10.2016
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Year of Publication 12.10.2016
Patent
SYSTEM OF ELECTRONIC MODULES HAVING A REDUNDANT CONFIGURATION
KIELBIK, RAFAL, NAPIERALSKI, ANDRZEJ, HALAGAN, KRZYSZTOF, ZATORSKI, WITOLD, ULANSKI, JACEK, PAKULA, TADEUSZ, JUNG, JAROSLAW, POLANOWSKI, PIOTR
Year of Publication 12.10.2016
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Year of Publication 12.10.2016
Patent
Machine parallel to the reduced number of connections between the logic systems
HAŁAGAN KRZYSZTOF, NAPIERALSKI ANDRZEJ, JUNG JAROSŁAW, ULAŃSKI JACEK, POLANOWSKI PIOTR, ZATORSKI WITOLD, KIEŁBIK RAFAŁ, PAKUŁA TADEUSZ
Year of Publication 30.11.2017
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Year of Publication 30.11.2017
Patent
Panel with electronic circuits and a set of panels
HAŁAGAN KRZYSZTOF, NAPIERALSKI ANDRZEJ, JUNG JAROSŁAW, ULAŃSKI JACEK, POLANOWSKI PIOTR, ZATORSKI WITOLD, KIEŁBIK RAFAŁ, PAKUŁA TADEUSZ
Year of Publication 30.11.2016
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Year of Publication 30.11.2016
Patent
Parallel machine with reduced number of connections between logic circuits
HAŁAGAN KRZYSZTOF, NAPIERALSKI ANDRZEJ, JUNG JAROSŁAW, ULAŃSKI JACEK, POLANOWSKI PIOTR, ZATORSKI WITOLD, KIEŁBIK RAFAŁ, PAKUŁA TADEUSZ
Year of Publication 24.10.2016
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Year of Publication 24.10.2016
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System of electronic modules with redundant configuration
NAPIERALSKI ANDRZEJ, ULA SKI JACEK, KIE BIK RAFA, POLANOWSKI PIOTR, ZATORSKI WITOLD, JUNG JAROS AW
Year of Publication 13.04.2015
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Year of Publication 13.04.2015
Patent
Machine parallel to the reduced number of connections between the logic systems
NAPIERALSKI ANDRZEJ, ULA SKI JACEK, KIE BIK RAFA, POLANOWSKI PIOTR, ZATORSKI WITOLD, JUNG JAROS AW
Year of Publication 13.04.2015
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Year of Publication 13.04.2015
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Machine parallel to the operating cells placed in the surface-centred network nods
NAPIERALSKI ANDRZEJ, ULA SKI JACEK, KIE BIK RAFA, POLANOWSKI PIOTR, ZATORSKI WITOLD, JUNG JAROS AW
Year of Publication 13.04.2015
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Year of Publication 13.04.2015
Patent
Panel with electronic circuits and a set of panels
NAPIERALSKI ANDRZEJ, ULA SKI JACEK, KIE BIK RAFA, POLANOWSKI PIOTR, ZATORSKI WITOLD, JUNG JAROS AW
Year of Publication 13.04.2015
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Year of Publication 13.04.2015
Patent