Capping poly channel pillars in stacked circuits
Damarla, Gowrisankar, Lindsay, Roger, Lu, Jin, Bian, Zailong, Srinivasan, Prasanna, Ramalingam, Shyam, Li, Hongqi
Year of Publication 11.06.2019
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Year of Publication 11.06.2019
Patent
Conductive structures, wordlines and transistors
Bian, Zailong, Gehrke, Thomas, Guha, Jaydip, Goswami, Jaydeb, Hu, Yushi, Blomiley, Eric R
Year of Publication 04.12.2018
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Year of Publication 04.12.2018
Patent
Conductive Structures, Wordlines and Transistors
Bian, Zailong, Gehrke, Thomas, Guha, Jaydip, Goswami, Jaydeb, Hu, Yushi, Blomiley, Eric R
Year of Publication 21.06.2018
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Year of Publication 21.06.2018
Patent
CONDUCTIVE STRUCTURES, WORDLINES AND TRANSISTORS
Bian, Zailong, Gehrke, Thomas, Guha, Jaydip, Goswami, Jaydeb, Hu, Yushi, Blomiley, Eric R
Year of Publication 17.05.2018
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Year of Publication 17.05.2018
Patent
Conductive structures, wordlines and transistors
Bian, Zailong, Gehrke, Thomas, Guha, Jaydip, Goswami, Jaydeb, Hu, Yushi, Blomiley, Eric R
Year of Publication 15.05.2018
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Year of Publication 15.05.2018
Patent
METHOD FOR FORMING A METAL CAP IN A SEMICONDUCTOR MEMORY DEVICE
Balakrishnan Muralikrishnan, Li Hongqi, Bian Zailong, Ramalingam Shyam, Lu Jin, Damarla Gowrisankar, Zhu Xiaoyun
Year of Publication 11.05.2017
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Year of Publication 11.05.2017
Patent
Method for forming a metal cap in a semiconductor memory device
Balakrishnan Muralikrishnan, Li Hongqi, Bian Zailong, Ramalingam Shyam, Lu Jin, Damarla Gowrisankar, Zhu Xiaoyun
Year of Publication 21.02.2017
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Year of Publication 21.02.2017
Patent