Direct Observation of Fluctuations in the Number and Individual Electronic Properties of Interface Traps in Nanoscale Metal--Oxide--Semiconductor Field-Effect Transistors
Tsuchiya, Toshiaki, Mori, Yuki, Morimura, Yuta, Mogami, Tohru, Ohji, Yuzuru
Published in Japanese Journal of Applied Physics (01.06.2010)
Published in Japanese Journal of Applied Physics (01.06.2010)
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Journal Article
Impact of Activation Annealing Temperature on the Performance, Negative Bias Temperature Instability, and Time-to-Dielectric Breakdown Lifetime of High-k/Metal Gate Stack p-Type Metal–Oxide–Semiconductor Field Effect Transistors
Sato, Motoyuki, Aoyama, Takayuki, Nara, Yasuo, Ohji, Yuzuru
Published in Japanese Journal of Applied Physics (01.04.2009)
Published in Japanese Journal of Applied Physics (01.04.2009)
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Journal Article
Study of a Negative Threshold Voltage Shift in Positive Bias Temperature Instability and a Positive Threshold Voltage Shift the Negative Bias Temperature Instability of Yttrium-Doped HfO2 Gate Dielectrics
Sato, Motoyuki, Kamiyama, Satoshi, Matsuki, Takeo, Ishikawa, Dai, Ono, Tetsuro, Morooka, Tetsu, Yugami, Jiro, Ikeda, Kazuto, Ohji, Yuzuru
Published in Jpn J Appl Phys (01.04.2010)
Published in Jpn J Appl Phys (01.04.2010)
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Journal Article
Ultralow-Thermal-Budget CMOS Process Using Flash-Lamp Annealing for 45 nm Metal/High- k FETs
Ootsuka, F., Katakami, A., Shirai, K., Watanabe, T., Nakata, H., Kitajima, M., Aoyama, T., Eimori, T., Nara, Y., Ohji, Y., Tanjyo, M.
Published in IEEE transactions on electron devices (01.04.2008)
Published in IEEE transactions on electron devices (01.04.2008)
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A proposal of new concept milli-second annealing: Flexibly-shaped-pulse flash lamp annealing (FSP-FLA) for fabrication of ultra shallow junction with improvement of metal gate high-k CMOS performance
Onizawa, T., Shinich Kato, Aoyama, T., Yasuo Nara, Yuzuru Ohji
Published in 2008 Symposium on VLSI Technology (01.06.2008)
Published in 2008 Symposium on VLSI Technology (01.06.2008)
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Conference Proceeding
Impact of the different nature of interface defect states on the NBTI and 1/f noise of high-k / metal gate pMOSFETs between (100) and (110) crystal orientations
Sato, M., Sugita, Y., Aoyama, T., Yasuo Nara, Yuzuru Ohji
Published in 2008 Symposium on VLSI Technology (01.06.2008)
Published in 2008 Symposium on VLSI Technology (01.06.2008)
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Conference Proceeding
Cathode Electron Injection Breakdown Model and Time Dependent Dielectric Breakdown Lifetime Prediction in High-k/Metal Gate Stack p-Type Metal–Oxide–Silicon Field Effect Transistors
Sato, Motoyuki, Tamura, Chihiro, Yamabe, Kikuo, Shiraishi, Kenji, Miyazaki, Seiichi, Yamada, Keisaku, Hasunuma, Ryu, Aoyama, Takayuki, Nara, Yasuo, Ohji, Yuzuru
Published in Japanese Journal of Applied Physics (01.05.2008)
Published in Japanese Journal of Applied Physics (01.05.2008)
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Theoretical approach and precise description of PBTI in high-k gate dielectrics based on electron trap in pre-existing and stress-induced defects
Shimokawa, J., Sato, M., Suzuki, C., Nakamura, M., Ohji, Y.
Published in 2009 IEEE International Reliability Physics Symposium (01.01.2009)
Published in 2009 IEEE International Reliability Physics Symposium (01.01.2009)
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Conference Proceeding
Properties of Ruthenium Films Prepared by Liquid Source Metalorganic Chemical Vapor Deposition Using Ru(EtCp) 2 with Tetrahydrofuran Solvent
Nabatame, Toshihide, Hiratani, Masahiko, Kadoshima, Masaru, Shimamoto, Yasuhiro, Matsui, Yuichi, Ohji, Yuzuru, Asano, Isamu, Fujiwara, Tetsuo, Suzuki, Takaaki
Published in Japanese Journal of Applied Physics (15.11.2000)
Published in Japanese Journal of Applied Physics (15.11.2000)
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Suppression of Boron Penetration from Source/Drain-Extension to Improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65-nm Node CMOS and Beyond
Hayashi, Takashi, Yamashita, Tomohiro, Shiga, Katsuya, Hayashi, Kiyoshi, Oda, Hidekazu, Eimori, Takahisa, Inuishi, Masahide, Ohji, Yuzuru
Published in Japanese Journal of Applied Physics (01.04.2005)
Published in Japanese Journal of Applied Physics (01.04.2005)
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Journal Article
Effective-Work-Function Control by Varying the TiN Thickness in Poly-Si/TiN Gate Electrodes for Scaled High- k CMOSFETs
Kadoshima, M., Matsuki, T., Miyazaki, S., Shiraishi, K., Chikyo, T., Yamada, K., Aoyama, T., Nara, Y., Ohji, Y.
Published in IEEE electron device letters (01.05.2009)
Published in IEEE electron device letters (01.05.2009)
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Journal Article
Proposal of Single Metal/Dual High-κ Devices for Aggressively Scaled CMISFETs With Precise Gate Profile Control
MISE, Nobuyuki, MOROOKA, Tetsu, EIMORI, Takahisa, ONO, Tetsuo, SATO, Motoyuki, KAMIYAMA, Satoshi, NARA, Yasuo, OHJI, Yuzuru
Published in IEEE transactions on electron devices (2009)
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Published in IEEE transactions on electron devices (2009)
Journal Article
Impact on Performance, Positive Bias Temperature Instability, and Time-Dependent Dielectric Dreakdown of n-Type Field Effect Transistors Incorporating Mg into HfSiON Gate Dielectrics
Sato, Motoyuki, Nabatame, Toshihide, Aoyama, Takayuki, Nara, Yasuo, Ohji, Yuzuru
Published in Japanese Journal of Applied Physics (01.05.2009)
Published in Japanese Journal of Applied Physics (01.05.2009)
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Journal Article
Simplified Surface Reaction Model of SF 6 /CHF 3 Plasma Etching of SiN Film
Iwakoshi, Takehisa, Aoyama, Takayuki, Nara, Yasuo, Ohji, Yuzuru
Published in Japanese Journal of Applied Physics (01.08.2009)
Published in Japanese Journal of Applied Physics (01.08.2009)
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Journal Article
High-k/metal gate stack technology for advanced CMOS
Nara, Y., Ootsuka, F., Inumiya, S., Ohji, Y.
Published in 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings (2006)
Published in 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings (2006)
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Conference Proceeding