Damage-free CMP towards 32nm-node porous low-k (k = 1.6)/Cu integration
Kondo, S., Yoon, B.U., Lee, S.G., Tokitoh, S., Misawa, K., Yoshie, T., Ohashi, N., Kobayashi, N.
Published in Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004 (2004)
Published in Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004 (2004)
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Highly reliable Cu interconnect strategy for 10nm node logic technology and beyond
Kim, R.-H, Kim, B. H., Matsuda, T., Kim, J. N., Baek, J. M., Lee, J. J., Cha, J. O., Hwang, J. H., Yoo, S. Y., Chung, K.-M, Park, K. H., Choi, J. K., Lee, E. B., Nam, S. D., Cho, Y. W., Choi, H. J., Kim, J. S., Jung, S. Y., Lee, D. H., Kim, I. S., Park, D. W., Lee, H. B., Ahn, S. H., Park, S. H., Kim, M.-C, Yoon, B. U., Paak, S. S., Lee, N.-I, Ku, J.-H, Yoon, J. S., Kang, H.-K, Jung, E. S.
Published in 2014 IEEE International Electron Devices Meeting (01.12.2014)
Published in 2014 IEEE International Electron Devices Meeting (01.12.2014)
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Low-pressure CMP for 300-mm ultra low-k (k=1.6-1.8)/Cu integration
Kondo, S., Yoon, B.U., Tokitoh, S., Misawa, K., Sone, S., Shin, H.J., Ohashi, N., Kobayashi, N.
Published in IEEE International Electron Devices Meeting 2003 (2003)
Published in IEEE International Electron Devices Meeting 2003 (2003)
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Low-pressure CMP for reliable porous low-k/Cu integration
Kondo, S., Tokitoh, S., Yoon, B.U., Namiki, A., Sone, A., Ohashi, N., Misawa, K., Sone, S., Shin, H.J., Yoshie, T., Yoneda, K., Shimada, M., Ogawa, S., Matsumoto, I., Kobayashi, N.
Published in Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695) (2003)
Published in Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695) (2003)
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Enhancement in electrical via-yield of porous low-k/Cu integration by reducing CMP pressure
Tokitoh, S., Kondo, S., Yoon, B.U., Namiki, A., Inukai, K., Misawa, K., Sone, S., Shin, H.J., Matsubara, Y., Ohashi, N., Kobayashi, N.
Published in Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729) (2004)
Published in Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729) (2004)
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PECVD low-k SiOC (k=2.8) as a cap layer for 200nm pitch Cu interconnect using porous low-k dielectrics (k=2.3)
Lee, S.G., Yoshie, T., Sudo, Y., Soda, E., Yoneda, K., Yoon, B.U., Kabayashi, H., Kageyama, S., Misawa, K., Kondo, S., Nasuno, T., Matsubara, Y., Ohashi, N., Kobayashi, N.
Published in Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729) (2004)
Published in Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729) (2004)
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Improved planarization method using sandwiched hard layer (SHaL) CMP
Kim, J.Y., Yoon, B.U., Hah, S.R., Moon, J.T., Lee, S.I.
Published in ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) (1999)
Published in ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) (1999)
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Impacts of high modulus ultra low-k/Cu 300 mm-wafer integration for 65 nm technology node and beyond
Sone, S., Ohashi, N., Shin, H.J., Misawa, K., Kaji, N., Inukai, K., Matsushita, A., Sudou, K., Tokitoh, S., Kondo, S., Yoon, B.U., Yoneda, K., Yoshie, T., Ohtsuka, N., Okamura, H., Toyoda, Y., Shoji, F., Nasuno, T., Shimada, M., Ogawa, S., Matsumoto, I., Kobayashi, N.
Published in 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) (2003)
Published in 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) (2003)
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