A pseudo-lucky electron model for simulation of electron gate current in submicron NMOSFET's
Hasnat, K., Yeap, C.-F., Jallepalli, S., Shih, W.-K., Hareland, S.A., Agostinelli, V.M., Tasch, A.F., Maziar, C.M.
Published in IEEE transactions on electron devices (01.08.1996)
Published in IEEE transactions on electron devices (01.08.1996)
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Journal Article
A Monte Carlo Study of Electron Transport in Silicon nMOSFET Inversion Layers
Shih, W.-K., Jallepalli, S., Yeap, C.-F., Rashed, M., Maziar, C. M., Tasch, A. F.
Published in VLSI design (Yverdon, Switzerland) (01.01.1998)
Published in VLSI design (Yverdon, Switzerland) (01.01.1998)
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Journal Article
A dual core oxide 8T SRAM cell with low Vccmin and dual voltage supplies in 45nm triple gate oxide and multi Vt CMOS for very high performance yet low leakage mobile SoC applications
Ping Liu, Wang, J, Phan, M, Garg, M, Zhang, R, Cassier, A, Chua-Eoan, L, Andreev, B, Weyland, S, Ekbote, S, Han, M, Fischer, J, Yeap, Geoffrey C.-F, Ping-Wei Wang, Li, Q, Hou, C S, Lee, S B, Wang, Y F, Lin, S S, Cao, M, Mii, Y J
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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Conference Proceeding
A computationally efficient model for inversion layer quantization effects in deep submicron N-channel MOSFETs
Hareland, S.A., Krishnamurthy, S., Jallepalli, S., Yeap, C.-F., Hasnat, K., Tasch, A.F., Maziar, C.M.
Published in Proceedings of International Electron Devices Meeting (1995)
Published in Proceedings of International Electron Devices Meeting (1995)
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Conference Proceeding
Analysis of quantization effects in silicon (100) inversion layers using a Monte Carlo tool
Shih, W.-K., Jallepalli, S., Yeap, C.-F., Rashed, M., Maziar, C.M., Tasch, A.F.
Published in Proceedings of the Eleventh Biennial University/Government/ Industry Microelectronics Symposium (1995)
Published in Proceedings of the Eleventh Biennial University/Government/ Industry Microelectronics Symposium (1995)
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Conference Proceeding
Two-dimensional energy-dependent substrate current models for deep submicron MOSFETs
Yeap, C.-F., Hasnat, K., Agostinelli, V.M., Bordelon, T.J., Jallepalli, S., Wang, X.L., Maziar, C.M., Tasch, A.F.
Published in Proceedings of International Workshop on Numerical Modeling of processes and Devices for Integrated Circuits: NUPAD V (1994)
Published in Proceedings of International Workshop on Numerical Modeling of processes and Devices for Integrated Circuits: NUPAD V (1994)
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Conference Proceeding
Ultra-thin decoupled plasma nitridation (DPN) oxynitride gate dielectric for 80-nm advanced technology
Tseng, H.-H., Jeon, Y., Abramowitz, P., Luo, T.-Y., Hebert, L., Lee, J.J., Jiang, J., Tobin, P.J., Yeap, G.C.F., Moosa, M., Alvis, J., Anderson, S.G.H., Cave, N., Chua, T.C., Hegedus, A., Miner, G., Jeon, J., Sultan, A.
Published in IEEE electron device letters (01.12.2002)
Published in IEEE electron device letters (01.12.2002)
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Journal Article
A computationally efficient model for inversion layer quantization effects in deep submicron N-channel MOSFETs
Hareland, S.A., Krishnamurthy, S., Jallepalli, S., Choh-Fei Yeap, Hasnat, K., Tasch, A.F., Maziar, C.M.
Published in IEEE transactions on electron devices (01.01.1996)
Published in IEEE transactions on electron devices (01.01.1996)
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Journal Article
Impact of tunnel currents and channel resistance on thecharacterization of channel inversion layer charge and polysilicon-gatedepletion of sub-20-A gate oxide MOSFETs
Ahmed, K, Ibok, E, Yeap, G C-F, Xiang, Qi, Ogle, B, Wortman, J J, Hauser, J R
Published in IEEE transactions on electron devices (01.08.1999)
Published in IEEE transactions on electron devices (01.08.1999)
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Journal Article
A two-dimensional model for predicting substrate current in submicrometer MOSFETs
Agostinelli, V.M., Bordelon, T.J., Wang, X.L., Yeap, C.F., Tasch, A.F., Maziar, C.M.
Published in IEEE transactions on electron devices (01.11.1992)
Published in IEEE transactions on electron devices (01.11.1992)
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Journal Article
Thermionic emission model of electron gate current in submicron NMOSFETs
Hasnat, K., Choh-Fei Yeap, Jallepalli, S., Hareland, S.A., Shih, W.-K., Agostinelli, V.M., Tasch, A.F., Maziar, C.M.
Published in IEEE transactions on electron devices (01.01.1997)
Published in IEEE transactions on electron devices (01.01.1997)
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Journal Article
INTEGRATED CIRCUIT DEVICE AND METHOD THEREFOR
JAMES, DAVID BURNETT, GEOFFREY, C-F YEAP, PAUL, A. GRUDOWSKI, SRINIVAS, JALLEPALLI, RANA, P. SINGH, YONGJOO, JEON
Year of Publication 08.10.2003
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Year of Publication 08.10.2003
Patent
Impact of tunnel currents and channel resistance on the characterization of channel inversion layer charge and polysilicon-gate depletion of sub-20-Aa gate oxide MOSFETs
Ahmed, K, Ibok, E, Yeap, GC-F, Xiang, Qi, Ogle, B, Wortman, J J, Hauser, J R
Published in IEEE transactions on electron devices (01.01.1999)
Published in IEEE transactions on electron devices (01.01.1999)
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Journal Article
Integrated circuit device and method therefor
JALLEPALLI, SRINIVAS, JEON, YONGJOO, BURNETT, JAMES DAVID, YEAP, GEOFFREY C-F, SINGH, RANA P.
Year of Publication 21.06.2007
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Year of Publication 21.06.2007
Patent