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Integrating assertion-based verification into system-level synthesis methodology
by
Hessabi, S.
,
Gharehbaghi, A.M.
,
Yaran
,
B.H
.
,
Goudarzi, M.
Published in
Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004
(2004)
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Applying cycle-based simulation technique to VITAL as a VHDL gate level standard
by
Yaran
,
B.H
.
,
Rahmati, D.
,
Zebardast, A.S.
Published in
Canadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings (Cat. No.01TH8555)
(2001)
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IEEE Xplore Digital Library
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