Search Results - "Yang, Chung-Jay" :: K.UTB vyhledávací portál

A High-Throughput Trellis-Based Layered Decoding Architecture for Non-Binary LDPC Codes Using Max-Log-QSPA

by UENG, Yeong-Luh, LIAO, Kuo-Hsuan, CHOU, Hsueh-Chih, YANG, Chung-Jay
Published in IEEE transactions on signal processing (01.06.2013)

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An Efficient Multi-Standard LDPC Decoder Design Using Hardware-Friendly Shuffled Decoding

by Ueng, Yeong-Luh, Yang, Bo-Jhang, Yang, Chung-Jay, Lee, Huang-Chang, Yang, Jeng-Da
Published in IEEE transactions on circuits and systems. I, Regular papers (01.03.2013)

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An Efficient Layered Decoding Architecture for Nonbinary QC-LDPC Codes

by Ueng, Yeong-Luh, Leong, Chen-Yap, Yang, Chung-Jay, Cheng, Chung-Chao, Liao, Kuo-Hsuan, Chen, Shu-Wei
Published in IEEE transactions on circuits and systems. I, Regular papers (01.02.2012)

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Processing-Task Arrangement for a Low-Complexity Full-Mode WiMAX LDPC Codec

by Wang, Yu-Luen, Ueng, Yeong-Luh, Peng, Chien-Lien, Yang, Chung-Jay
Published in IEEE transactions on circuits and systems. I, Regular papers (01.02.2011)

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A Multimode Shuffled Iterative Decoder Architecture for High-Rate RS-LDPC Codes

by Ueng, Yeong-Luh, Yang, Chung-Jay, Wang, Kuan-Chieh, Chen, Chun-Jung
Published in IEEE transactions on circuits and systems. I, Regular papers (01.10.2010)

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Jointly Designed Architecture-Aware LDPC Convolutional Codes and Memory-Based Shuffled Decoder Architecture

by UENG, Yeong-Luh, WANG, Yu-Luen, KAN, Li-Sheng, YANG, Chung-Jay, SU, Yung-Hsiang
Published in IEEE transactions on signal processing (01.08.2012)

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A shuffled message-passing decoding method for memory-based LDPC decoders

by Yeong-Luh Ueng, Chung-Jay Yang, Chun-Jung Chen
Published in 2009 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2009)

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VLSI decoding architecture with improved convergence speed and reduced decoding latency for irregular LDPC codes in WiMAX

by Ueng, Yeong-Luh, Yang, Chung-Jay, Wu, Zong-Cheng, Wu, Chen-Eng, Wang, Yu-Lun
Published in 2008 IEEE International Symposium on Circuits and Systems (01.01.2008)

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A low-complexity LDPC decoder architecture for WiMAX applications

by Yu-Luen Wang, Yeong-Luh Ueng, Chian-Lien Peng, Chung-Jay Yang
Published in Proceedings of 2011 International Symposium on VLSI Design, Automation and Test (01.04.2011)

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A selective-input non-binary LDPC decoder architecture

by Yeong-Luh Ueng, Chung-Jay Yang, Shu-Wei Chen, Wei-Xuan Wu
Published in 2011 International SoC Design Conference (01.11.2011)

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Selective-mapping type peak power reduction techniques for turbo coded OFDM

by Mao-Chao Lin, Yung-Chih Tsai, Chung-Jay Yang
Published in 2005 International Conference on Wireless Networks, Communications and Mobile Computing (2005)

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