Junctionless versus inversion-mode lateral semiconductor nanowire transistors
Veloso, A, Matagne, P, Simoen, E, Kaczer, B, Eneman, G, Mertens, H, Yakimets, D, Parvais, B, Mocuta, D
Published in Journal of physics. Condensed matter (26.09.2018)
Published in Journal of physics. Condensed matter (26.09.2018)
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Journal Article
Holisitic device exploration for 7nm node
Raghavan, P., Bardon, M. Garcia, Jang, D., Schuddinck, P., Yakimets, D., Ryckaert, J., Mercha, A., Horiguchi, N., Collaert, N., Mocuta, A., Mocuta, D., Tokei, Z., Verkest, D., Thean, A., Steegen, A.
Published in 2015 IEEE Custom Integrated Circuits Conference (CICC) (01.09.2015)
Published in 2015 IEEE Custom Integrated Circuits Conference (CICC) (01.09.2015)
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Conference Proceeding
Vertical device architecture for 5nm and beyond: Device & circuit implications
Thean, A. V.-Y, Yakimets, D., Huynh Bao, T., Schuddinck, P., Sakhare, S., Bardon, M. Garcia, Sibaja-Hernandez, A., Ciofi, I., Eneman, G., Veloso, A., Ryckaert, J., Raghavan, P., Mercha, A., Mocuta, A., Tokei, Z., Verkest, D., Wambacq, P., De Meyer, K., Collaert, N.
Published in 2015 Symposium on VLSI Technology (VLSI Technology) (01.06.2015)
Published in 2015 Symposium on VLSI Technology (VLSI Technology) (01.06.2015)
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Conference Proceeding
Journal Article
Novel forksheet device architecture as ultimate logic scaling device towards 2nm
Weckx, P., Ryckaert, J., Litta, E. Dentoni, Yakimets, D., Matagne, P., Schuddinck, P., Jang, D., Chehab, B., Baert, R., Gupta, M., Oniki, Y., Ragnarsson, L.-A., Horiguchi, N., Spessot, A., Verkest, D.
Published in 2019 IEEE International Electron Devices Meeting (IEDM) (01.12.2019)
Published in 2019 IEEE International Electron Devices Meeting (IEDM) (01.12.2019)
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Conference Proceeding
Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology
Yakimets, D., Bardon, M. Garcia, Jang, D., Schuddinck, P., Sherazi, Y., Weckx, P., Miyaguchi, K., Parvais, B., Raghavan, P., Spessot, A., Verkest, D., Mocuta, A.
Published in 2017 IEEE International Electron Devices Meeting (IEDM) (01.12.2017)
Published in 2017 IEEE International Electron Devices Meeting (IEDM) (01.12.2017)
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Conference Proceeding
Limitations on Lateral Nanowire Scaling Beyond 7-nm Node
Das, Uttam Kumar, Garcia Bardon, M., Jang, D., Eneman, G., Schuddinck, P., Yakimets, D., Raghavan, P., Groeseneken, Guido
Published in IEEE electron device letters (01.01.2017)
Published in IEEE electron device letters (01.01.2017)
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Journal Article
Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires
Bardon, M. Garcia, Sherazi, Y., Schuddinck, P., Jang, D., Yakimets, D., Debacker, P., Baert, R., Mertens, H., Badaroglu, M., Mocuta, A., Horiguchi, N., Mocuta, D., Raghavan, P., Ryckaert, J., Spessot, A., Verkest, D., Steegen, A.
Published in 2016 IEEE International Electron Devices Meeting (IEDM) (01.12.2016)
Published in 2016 IEEE International Electron Devices Meeting (IEDM) (01.12.2016)
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Conference Proceeding
Device-, Circuit- & Block-level evaluation of CFET in a 4 track library
Schuddinck, P., Zografos, O., Weckx, P., Matagne, P., Sarkar, S., Sherazi, Y., Baert, R., Jang, D., Yakimets, D., Gupta, A., Parvais, B., Ryckaert, J., Verkest, D., Mocuta, A.
Published in 2019 Symposium on VLSI Technology (01.06.2019)
Published in 2019 Symposium on VLSI Technology (01.06.2019)
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Conference Proceeding
Power-performance Trade-offs for Lateral NanoSheets on Ultra-Scaled Standard Cells
Bardon, M. Garcia, Sherazi, Y., Jang, D., Yakimets, D., Schuddinck, P., Baert, R., Mertens, H., Mattii, L., Parvais, B., Mocuta, A., Verkest, D.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Conference Proceeding
(Invited) Vertical Nanowire FET Integration and Device Aspects
Veloso, Anabela, Altamirano-Sánchez, Efraín, Brus, Stephan, Chan, B. T., Cupak, Miroslav, Dehan, Morin, Delvaux, Christie, Devriendt, Katia, Eneman, Geert, Ercken, Monique, Huynh-Bao, Trong, Ivanov, Tsvetan, Matagne, Philippe, Merckling, Clement, Paraschiv, Vasile, Ramesh, Siva, Rosseel, Erik, Rynders, Luc, Sibaja-Hernandez, Arturo, Suhard, Samuel, Tao, Zheng, Vecchio, Emma, Waldron, Niamh, Yakimets, Dmitry, De Meyer, Kristin, Mocuta, Dan, Collaert, Nadine, Thean, Aaron
Published in ECS transactions (04.05.2016)
Published in ECS transactions (04.05.2016)
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Journal Article
Dimensioning for power and performance under 10nm: The limits of FinFETs scaling
Bardon, M. Garcia, Schuddinck, P., Raghavan, P., Jang, D., Yakimets, D., Mercha, A., Verkest, D., Thean, A.
Published in 2015 International Conference on IC Design & Technology (ICICDT) (01.06.2015)
Published in 2015 International Conference on IC Design & Technology (ICICDT) (01.06.2015)
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Conference Proceeding
Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node
Gupta, A., Mertens, H., Tao, Z., Demuynck, S., Bommels, J., Arutchelvan, G., Devriendt, K., Pedreira, O. Varela, Ritzenthaler, R., Wang, S., Radisic, D., Kenis, K., Teugels, L., Sebaai, F., Lorant, C., Jourdan, N., Chan, B. T., Zahedmanesh, H., Subramanian, S., Schleicher, F., Hopf, T., Peter, A., Rassoul, N., Debruyn, H., Demonie, I., Siew, Y., Chiarella, T., Briggs, B., Zhou, D., Rosseel, E., De Keersgieter, A., Capogreco, E., Litta, E. Dentoni, Boccardi, G., Baudot, S., Mannaert, G., Bontemps, N., Sepulveda, A., Mertens, S., Kim, M. S., Dupuy, E., Vandersmissen, K., Paolillo, S., Yakimets, D., Chehab, B., Favia, P., Drijbooms, C., Cousserier, J., Jaysankar, M., Lazzarino, F., Morin, P., Sanchez, E., Mitard, J., Wilson, C., Holsteyns, F., Tokei, Z., Horiguchi, N.
Published in 2020 IEEE Symposium on VLSI Technology (01.06.2020)
Published in 2020 IEEE Symposium on VLSI Technology (01.06.2020)
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Conference Proceeding
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies
Bao, T. Huynh, Yakimets, D., Ryckaert, J., Ciofi, I., Baert, R., Veloso, A., Boemmels, J., Collaert, N., Roussel, P., Demuynck, S., Raghavan, P., Mercha, A., Tokei, Z., Verkest, D., Thean, A. V-Y, Wambacq, P.
Published in 2014 44th European Solid State Device Research Conference (ESSDERC) (01.09.2014)
Published in 2014 44th European Solid State Device Research Conference (ESSDERC) (01.09.2014)
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Conference Proceeding
Lateral NWFET optimization for beyond 7nm nodes
Yakimets, D., Jang, D., Raghavan, P., Eneman, G., Mertens, H., Schuddinck, P., Mallik, A., Bardon, M. Garcia, Collaert, N., Mercha, A., Verkest, D., Thean, A., De Meyer, K.
Published in 2015 International Conference on IC Design & Technology (ICICDT) (01.06.2015)
Published in 2015 International Conference on IC Design & Technology (ICICDT) (01.06.2015)
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Conference Proceeding
Lateral versus vertical gate-all-around FETs for beyond 7nm technologies
Yakimets, D., Bao, T. Huynh, Bardon, M. Garcia, Dehan, M., Collaert, N., Mercha, A., Tokei, Z., Thean, A., Verkest, D., De Meyer, K.
Published in 72nd Device Research Conference (01.06.2014)
Published in 72nd Device Research Conference (01.06.2014)
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Conference Proceeding
(Invited) Heterogeneous Nano- to Wide-Scale Co-Integration of Beyond-Si and Si CMOS Devices to Enhance Future Electronics
Thean, Aaron, Collaert, Nadine, Radu, Iuliana P., Waldron, Niamh, Merckling, Clement, Witters, Liesbeth, Loo, Roger, Mitard, Jerome, Rooyackers, Rita, Vandooren, Anne, Verhulst, A., Veloso, Anabela, Yakimets, D., Bao, T. Huynh, Chiappe, Danielle, Vaysset, A., Zografos, O., Caymax, Matty, Huyghebaert, C, Barla, Kathy, Steegen, A.
Published in ECS transactions (31.03.2015)
Published in ECS transactions (31.03.2015)
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Journal Article
Layout-induced stress effects in 14nm & 10nm FinFETs and their impact on performance
Bardon, M. Garcia, Moroz, V., Eneman, G., Schuddinck, P., Dehan, M., Yakimets, D., Jang, D., Van der Plas, G., Mercha, A., Thean, A., Verkest, D., Steegen, A.
Published in 2013 Symposium on VLSI Technology (01.06.2013)
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Published in 2013 Symposium on VLSI Technology (01.06.2013)
Conference Proceeding
Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node
Sakhare, S., Perumkunnil, M., Bao, T. Huynh, Rao, S., Kim, W., Crotti, D., Yasin, F., Couet, S., Swerts, J., Kundu, S., Yakimets, D., Baert, R., Oh, HR, Spessot, A., Mocuta, A., Kar, G. Sankar, Furnemont, A.
Published in 2018 IEEE International Electron Devices Meeting (IEDM) (01.12.2018)
Published in 2018 IEEE International Electron Devices Meeting (IEDM) (01.12.2018)
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Conference Proceeding
Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration
Mertens, H., Ritzenthaler, R., Pena, V., Santoro, G., Kenis, K., Schulze, A., Litta, E. D., Chew, S. A., Devriendt, K., Chiarella, R., Demuynck, S., Yakimets, D., Jang, D., Spessot, A., Eneman, G., Dangol, A., Lagrain, P., Bender, H., Sun, S., Korolik, M., Kioussis, D., Kim, M., Bu, Chen, S. C., Cogorno, M., Devrajan, J., Machillot, J., Yoshida, N., Kim, N., Barla, K., Mocuta, D., Horiguchi, N.
Published in 2017 IEEE International Electron Devices Meeting (IEDM) (01.12.2017)
Published in 2017 IEEE International Electron Devices Meeting (IEDM) (01.12.2017)
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Conference Proceeding
The impact of sequential-3D integration on semiconductor scaling roadmap
Mallik, A., Vandooren, A., Witters, L., Walke, A., Franco, J., Sherazi, Y., Weckx, P., Yakimets, D., Bardon, M., Parvais, B., Debacker, P., Ku, B. W., Lim, S. K., Mocuta, A., Mocuta, D., Ryckaert, J., Collaert, N., Raghavan, P.
Published in 2017 IEEE International Electron Devices Meeting (IEDM) (01.12.2017)
Published in 2017 IEEE International Electron Devices Meeting (IEDM) (01.12.2017)
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Conference Proceeding