Process Engineering and Trap Distribution for Dielectric/Si Interfacial Layer in High-k Gated MOS Devices
Chang-Liao, Kuei-Shu, Fu, Chung-Hao, Lu, Chun-Chang, Chang, Yu-An, Hsu, Ya-Yin, Tsao, Che-Hao, Wang, Tien-Ko, Heh, Da-Wei, Li, Y.C., Tsai, Wen-Fa, Ai, Chi-Fong, Hou, Fu-Chung, Hsu, Yao-Tung
Published in ECS transactions (01.01.2011)
Published in ECS transactions (01.01.2011)
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Journal Article
A 0.7 nm EOT and low gate leakage current for MOS device with Ti/HfO2/Hf higher-k gate dielectric
Hao-Zhi Hong, Kuei-Shu Chang-Liao, Chung-Hao Fu, Chen-Chien Li, Ya-Yin Hsu, Tien-Ko Wang
Published in 2011 International Semiconductor Device Research Symposium (ISDRS) (01.12.2011)
Published in 2011 International Semiconductor Device Research Symposium (ISDRS) (01.12.2011)
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Conference Proceeding
Process Engineering and Trap Distribution for Dielectric/Si Interfacial Layer in High-k Gated MOS Devices
Chang-Liao, Kuei-Shu, Fu, Chung-Hao, Lu, Chun-Chang, Chang, Yu-An, Hsu, Ya-Yin, Wang, Tien-Ko, Heh, Da-Wei
Published in Meeting abstracts (Electrochemical Society) (01.03.2011)
Published in Meeting abstracts (Electrochemical Society) (01.03.2011)
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Journal Article