Method of area compaction for integrated circuit layout design
Yu, Kathleen C, Hector, Scott D, Maziasz, Robert L, Stanley, Claudia A, Vasck, James E
Year of Publication 08.03.2011
Get full text
Year of Publication 08.03.2011
Patent
Semiconductor device having a multiple thickness interconnect
Yu, Kathleen C, Strozewski, Kirk J, Farkas, Janos, Sanchez, Hector, Lii, Yeong-Jyh T
Year of Publication 13.02.2007
Get full text
Year of Publication 13.02.2007
Patent
Method for forming a gate electrode having a metal
Adetutu, Olubunmi O, Michaelson, Lynne M, Yu, Kathleen C, Jones, Jr, Robert E
Year of Publication 18.04.2006
Get full text
Year of Publication 18.04.2006
Patent
Method for forming a semiconductor interconnect with multiple thickness
Yu, Kathleen C, Strozewski, Kirk J, Farkas, Janos, Sanchez, Hector, Lii, Yeong-Jyh T
Year of Publication 09.11.2004
Get full text
Year of Publication 09.11.2004
Patent
MULTIPLE THICKNESS SEMICONDUCTOR INTERCONNECT AND METHOD THEREFOR
YEONG-JYH, T. LII, KATHLEEN, C. YU, JANOS FARKAS, HECTOR SANCHEZ, KIRK, J. STROZEWSKI
Year of Publication 12.12.2003
Get full text
Year of Publication 12.12.2003
Patent
Multiple thickness semiconductor interconnect and method therefor
KIRK J. STROZEWSKI, JANOS FARKAS, HECTOR SANCHEZ, YEONG-JYH T. LII, KATHLEEN C. YU
Year of Publication 12.12.2003
Get full text
Year of Publication 12.12.2003
Patent
Method for forming a passivation layer for air gap formation and structure thereof
KIRK J. STROZEWSKI, BRADLEY P. SMITH, STANLEY MICHAEL FILIPIAK, JOHN C. FLAKE, TERRY G. SPARKS, YURI E. SOLOMENTSEV, YEONG-JYH T. LII, CINDY K. GOLDBERG, KATHLEEN C. YU
Year of Publication 01.07.2012
Get full text
Year of Publication 01.07.2012
Patent
Multiple thickness semiconductor interconnect and method therefor
KIRK J. STROZEWSKI, JANOS FARKAS, HECTOR SANCHEZ, YEONG-JYH T. LII, KATHLEEN C. YU
Year of Publication 11.02.2008
Get full text
Year of Publication 11.02.2008
Patent
Method for forming a passivation layer for air gap formation and structure thereof
SMITH, BRADLEY P, KIRK J. STROZEWSKI, FILIPIAK, STANLEY MICHAEL, FLAKE, JOHN C, GOLDBERG, CINDY K, LII, YEONG-JYH T, TERRY G. SPARKS, YURI E. SOLOMENTSEV, KATHLEEN C. YU
Year of Publication 01.08.2004
Get full text
Year of Publication 01.08.2004
Patent
METHOD FOR FORMING A GATE ELECTRODE HAVING A METAL
YU, KATHLEEN C, ADETUTU, OLUBUNMI O, JONES JR., ROBERT E, MICHAELSON, LYNNE M
Year of Publication 19.06.2013
Get full text
Year of Publication 19.06.2013
Patent
Method of area compaction for integrated circuit layout design
YU KATHLEEN C, VASCK JAMES E, HECTOR SCOTT D, STANLEY CLAUDIA A, MAZIASZ ROBERT L
Year of Publication 08.03.2011
Get full text
Year of Publication 08.03.2011
Patent
METHOD OF AREA COMPACTION FOR INTEGRATED CIRCUIT LAYOUT DESIGN
YU KATHLEEN C, VASCK JAMES E, HECTOR SCOTT D, STANLEY CLAUDIA A, MAZIASZ ROBERT L
Year of Publication 18.06.2009
Get full text
Year of Publication 18.06.2009
Patent
METHOD FOR FORMING A GATE ELECTRODE HAVING A METAL
YU, KATHLEEN C, ADETUTU, OLUBUNMI O, MICHAELSON, LYNNE M, JONES, ROBERT E., JR
Year of Publication 06.05.2009
Get full text
Year of Publication 06.05.2009
Patent