25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications
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Published in 2021 IEEE International Solid- State Circuits Conference (ISSCC) (13.02.2021)
Published in 2021 IEEE International Solid- State Circuits Conference (ISSCC) (13.02.2021)
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Conference Proceeding
Performance characterization of mixed-signal circuits using a ternary signal representation
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Published in 2004 International Conferce on Test (2004)
Published in 2004 International Conferce on Test (2004)
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Conference Proceeding
DSP-based statistical self test of on-chip converters
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Published in Proceedings. 21st VLSI Test Symposium, 2003 (2003)
Published in Proceedings. 21st VLSI Test Symposium, 2003 (2003)
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Conference Proceeding
A SRAM Core Architecture with Adaptive Cell Bias Scheme
Hak-soo Yu, Nam-Seog Kim, Young-Jae Son, Yong-Goel Kim, Hyo-Chang Kim, Uk-Rae Cho, Hyun-Geun Byun
Published in 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers (2006)
Published in 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers (2006)
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Conference Proceeding
Efficient loop-back testing of on-chip ADCs and DACs
Hak-soo Yu, Abraham, J.A., Sungbae Hwang, Jeongjin Roh
Published in Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003 (2003)
Published in Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003 (2003)
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Conference Proceeding