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"YEH CHUNN"
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"YEH CHUNN"
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REDUCED TRENCH PROFILE FOR A GATE
by
LIU QING
,
YEH CHUNN
,
CAI XIUYU
,
XIE RUILONG
Year of Publication
23.06.2016
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TRENCH EPITAXIAL GROWTH FOR A FINFET DEVICE HAVING REDUCED CAPACITANCE
by
LIU QING
,
YEH CHUNN
,
CAI XIUYU
,
XIE RUILONG
Year of Publication
23.06.2016
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LDMOS FINFET DEVICE AND METHOD OF MANUFACTURE USING A TRENCH CONFINED EPITAXIAL GROWTH PROCESS
by
LIU QING
,
YEH CHUNN
,
XIE RUILONG
,
CAI XIUYU
Year of Publication
09.06.2016
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Symmetrical extension junction formation with low-K spacer and dual epitaxial process in FinFET device
by
YAMASHITA TENKO
,
LIU ZUOGUANG
,
BASKER VEERARAGHAVAN S
,
YEH CHUNN
Year of Publication
07.06.2016
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Test macro for use with a multi-patterning lithography process
by
CHO JIN
,
YAMASHITA TENKO
,
YEH CHUNN
,
ZANG HUI
Year of Publication
31.05.2016
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Structure and Method to Form Passive Devices in ETSOI Process Flow
by
GUO DECHAO
,
CAI MING
,
YEH CHUNN
Year of Publication
15.05.2014
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Anchored stress-generating active semiconductor regions for semiconductor-on-insulator finfet
by
YAMASHITA TENKO
,
IYENGAR KRISHNA
,
BASKER VEERARAGHAVAN S
,
YEH CHUNN
Year of Publication
24.05.2016
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Non-lithographic hole pattern formation
by
TSENG CHIAHSUN
,
YIN YUNPENG
,
HORAK DAVID V
,
YEH CHUNN
Year of Publication
03.05.2016
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Integration of SMT in replacement gate FINFET process flow
by
GUO DECHAO
,
CAI MING
,
YEH CHUNN
Year of Publication
15.04.2014
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GATE STRUCTURE INTEGRATION SCHEME FOR FIN FIELD EFFECT TRANSISTORS
by
TSENG CHIAHSUN
,
YIN YUNPENG
,
HE HONG
,
YEH CHUNN
Year of Publication
28.04.2016
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Self-aligned contact process enabled by low temperature
by
TSENG CHIAHSUN
,
YIN YUNPENG
,
HE HONG
,
YEH CHUNN
Year of Publication
26.04.2016
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Buried local interconnect in finfet structure and method of fabricating same
by
YAMASHITA TENKO
,
BASKER VEERARAGHAVAN
,
YEH CHUNN
,
ZANG HUI
Year of Publication
26.04.2016
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MULTI-CHANNEL GATE-ALL-AROUND FET
by
LIU QING
,
YEH CHUNN
,
XIE RUILONG
,
CAI XIUYU
Year of Publication
21.04.2016
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LOCALIZED FIN WIDTH SCALING USING A HYDROGEN ANNEAL
by
YAMASHITA TENKO
,
MOCHIZUKI SHOGO
,
BASKER VEERARAGHAVAN S
,
YEH CHUNN
Year of Publication
21.04.2016
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Method for making a semiconductor device while avoiding nodules on a gate
by
LIU QING
,
WANG KEJIA
,
YEH CHUNN
,
XIE RUILONG
,
CAI XIUYU
Year of Publication
19.04.2016
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MULTI-GATE FIELD EFFECT TRANSISTOR DEVICES
by
YAMASHITA TENKO
,
BASKER VEERARAGHAVAN S
,
YEH CHUNN
Year of Publication
27.03.2014
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STACKED NANOWIRE FIELD EFFECT TRANSISTOR
by
YAMASHITA TENKO
,
BASKER VEERARAGHAVAN S
,
YEH CHUNN
Year of Publication
27.03.2014
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MULTI-GATE FIELD EFFECT TRANSISTOR DEVICES
by
YAMASHITA TENKO
,
BASKER VEERARAGHAVAN S
,
YEH CHUNN
Year of Publication
27.03.2014
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STACKED NANOWIRE FIELD EFFECT TRANSISTOR
by
YAMASHITA TENKO
,
BASKER VEERARAGHAVAN S
,
YEH CHUNN
Year of Publication
27.03.2014
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Stacked nanowire field effect transistor
by
YAMASHITA TENKO
,
BASKER VEERARAGHAVAN S
,
YEH CHUNN
Year of Publication
25.03.2014
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