Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature
Takahashi, R., Takata, H., Yasufuku, T., Fuketa, H., Takamiya, M., Nomura, M., Shinohara, H., Sakurai, T.
Published in IEEE transactions on circuits and systems. II, Express briefs (01.12.2012)
Published in IEEE transactions on circuits and systems. II, Express briefs (01.12.2012)
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Journal Article
12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics
Fuketa, Hiroshi, Hirairi, Koji, Yasufuku, Tadashi, Takamiya, Makoto, Nomura, Masahiro, Shinohara, Hirofumi, Sakurai, Takayasu
Published in IEEE/ACM International Symposium on Low Power Electronics and Design (01.08.2011)
Published in IEEE/ACM International Symposium on Low Power Electronics and Design (01.08.2011)
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Conference Proceeding
A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates
Fuketa, Hiroshi, Iida, Satoshi, Yasufuku, Tadashi, Takamiya, Makoto, Nomura, Masahiro, Shinohara, Hirofumi, Sakurai, Takayasu
Published in 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC) (05.06.2011)
Published in 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC) (05.06.2011)
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Conference Proceeding
Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS
Yasufuku, T., Iida, S., Fuketa, H., Hirairi, K., Nomura, M., Takamiya, M., Sakurai, T.
Published in IEEE/ACM International Symposium on Low Power Electronics and Design (01.08.2011)
Published in IEEE/ACM International Symposium on Low Power Electronics and Design (01.08.2011)
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Conference Proceeding
A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology
Maejima, Hiroshi, Kanda, Kazushige, Fujimura, Susumu, Takagiwa, Teruo, Ozawa, Susumu, Sato, Jumpei, Shindo, Yoshihiko, Sato, Manabu, Kanagawa, Naoaki, Musha, Junji, Inoue, Satoshi, Sakurai, Katsuaki, Morozumi, Naohito, Fukuda, Ryo, Shimizu, Yuui, Hashimoto, Toshifumi, Xu Li, Shimizu, Yuuki, Abe, Kenichi, Yasufuku, Tadashi, Minamoto, Takatoshi, Yoshihara, Hiroshi, Yamashita, Takahiro, Satou, Kazuhiko, Sugimoto, Takahiro, Kono, Fumihiro, Abe, Mitsuhiro, Hashiguchi, Tomoharu, Kojima, Masatsugu, Suematsu, Yasuhiro, Shimizu, Takahiro, Imamoto, Akihiro, Kobayashi, Naoki, Miakashi, Makoto, Yamaguchi, Kouichirou, Bushnaq, Sanad, Haibi, Hicham, Ogawa, Masatsugu, Ochi, Yusuke, Kubota, Kenro, Wakui, Taichi, Dong He, Weihan Wang, Minagawa, Hiroe, Nishiuchi, Tomoko, Hao Nguyen, Kwang-Ho Kim, Ken Cheah, Yee Koh, Feng Lu, Ramachandra, Venky, Rajendra, Srinivas, Choi, Steve, Payak, Keyur, Raghunathan, Namas, Georgakis, Spiros, Sugawara, Hiroshi, Seungpil Lee, Futatsuyama, Takuya, Hosono, Koji, Shibata, Noboru, Hisada, Toshiki, Kaneko, Tetsuya, Nakamura, Hiroshi
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
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Conference Proceeding
Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: [Formula Omitted]-Aware Dual Supply Voltage Technique
Fuketa, Hiroshi, Hirairi, Koji, Yasufuku, Tadashi, Takamiya, Makoto, Nomura, Masahiro, Shinohara, Hirofumi, Sakurai, Takayasu
Published in IEEE transactions on very large scale integration (VLSI) systems (01.06.2013)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.06.2013)
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Journal Article
Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: V rm DDmin -Aware Dual Supply Voltage Technique
Fuketa, Hiroshi, Hirairi, Koji, Yasufuku, Tadashi, Takamiya, Makoto, Nomura, Masahiro, Shinohara, Hirofumi, Sakurai, Takayasu
Published in IEEE transactions on very large scale integration (VLSI) systems (01.06.2013)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.06.2013)
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Journal Article
Device-circuit interactions in extremely low voltage CMOS designs (invited)
Fuketa, H., Yasufuku, T., Iida, S., Takamiya, M., Nomura, M., Shinohara, H., Sakurai, T.
Published in 2011 International Electron Devices Meeting (01.12.2011)
Published in 2011 International Electron Devices Meeting (01.12.2011)
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Conference Proceeding
Stretchable EMI Measurement Sheet With 8 x 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 μm Silicon CMOS LSIs for Electric and Magnetic Field Detection
ISHIDA, Koichi, MASUNAGA, Naoki, ZHIWEI ZHOU, YASUFUKU, Tadashi, SEKITANI, Tsuyoshi, ZSCHIESCHANG, Ute, KLAUK, Hagen, TAKAMIYA, Makoto, SOMEYA, Takao, SAKURAI, Takayasu
Published in IEEE journal of solid-state circuits (2010)
Published in IEEE journal of solid-state circuits (2010)
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Conference Proceeding
Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique
FUKETA, Hiroshi, HIRAIRI, Koji, YASUFUKU, Tadashi, TAKAMIYA, Makoto, NOMURA, Masahiro, SHINOHARA, Hirofumi, SAKURAI, Takayasu
Published in IEEE transactions on very large scale integration (VLSI) systems (2013)
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Published in IEEE transactions on very large scale integration (VLSI) systems (2013)
Journal Article
Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: V-Aware Dual Supply Voltage Technique
Fuketa, H., Hirairi, K., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H., Sakurai, T.
Published in IEEE transactions on very large scale integration (VLSI) systems (01.06.2013)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.06.2013)
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Journal Article
Stretchable EMI Measurement Sheet With 8 $\times$ 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18$\ \mu$m Silicon CMOS LSIs for Electric and Magnetic Field Detection
Ishida, Koichi, Masunaga, Naoki, Zhou, Zhiwei, Yasufuku, Tadashi, Sekitani, Tsuyoshi, Zschieschang, Ute, Klauk, Hagen, Takamiya, Makoto, Someya, Takao, Sakurai, Takayasu
Published in IEEE journal of solid-state circuits (01.01.2010)
Published in IEEE journal of solid-state circuits (01.01.2010)
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Journal Article
13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO
Hirairi, K., Okuma, Y., Fuketa, H., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H., Sakurai, T.
Published in 2012 IEEE International Solid-State Circuits Conference (01.02.2012)
Published in 2012 IEEE International Solid-State Circuits Conference (01.02.2012)
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Conference Proceeding
Through-Silicon Via Design for a 3-D Solid-State Drive System With Boost Converter in a Package
Johguchi, K, Hatanaka, T, Ishida, K, Yasufuku, T, Takamiya, M, Sakurai, T, Takeuchi, K
Published in IEEE transactions on components, packaging, and manufacturing technology (2011) (01.02.2011)
Published in IEEE transactions on components, packaging, and manufacturing technology (2011) (01.02.2011)
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Journal Article