Ultrahigh-speed InP/InGaAs DHPTs for OEMMICs
Kamitsuna, H., Matsuoka, Y., Yamahata, S., Shigekawa, N.
Published in IEEE transactions on microwave theory and techniques (01.10.2001)
Published in IEEE transactions on microwave theory and techniques (01.10.2001)
Get full text
Journal Article
Optimization of AlGaN-based spacer layer for InAlN/GaN interfaces
Akazawa, M., Gao, B., Hashizume, T., Hiroki, M., Yamahata, S., Shigekawa, N.
Published in Physica status solidi. C (01.03.2012)
Published in Physica status solidi. C (01.03.2012)
Get full text
Journal Article
A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector
Nosaka, H., Sano, E., Ishii, K., Ida, M., Kurishima, K., Yamahata, S., Shibata, T., Fukuyama, H., Yoneyama, M., Enoki, T., Muraguchi, M.
Published in IEEE journal of solid-state circuits (01.08.2004)
Published in IEEE journal of solid-state circuits (01.08.2004)
Get full text
Journal Article
Over 40 Gbit/s 16:1 multiplexer IC using InP/InGaAs HBT technology
Ishii, K., Nakajima, H., Nosaka, H., Ida, M., Kurishima, K., Yamahata, S., Enoki, T., Shibata, T.
Published in Electronics letters (12.06.2003)
Published in Electronics letters (12.06.2003)
Get full text
Journal Article
4-bit multiplexer/demultiplexer chip set for 40-Gbit/s optical communication systems
Ishii, K., Nosaka, H., Ida, M., Kurishima, K., Yamahata, S., Enoki, T., Shibata, T., Sano, E.
Published in IEEE transactions on microwave theory and techniques (01.11.2003)
Published in IEEE transactions on microwave theory and techniques (01.11.2003)
Get full text
Journal Article
Initial degradation of base-emitter junction in carbon-doped InP/InGaAs HBTs under bias and temperature stress
Kurishima, K., Yamahata, S., Nakajima, H., Ito, H., Watanabe, N.
Published in IEEE electron device letters (01.08.1998)
Published in IEEE electron device letters (01.08.1998)
Get full text
Journal Article
Over-30-GHz limiting amplifier ICs with small phase deviation for optical communication systems
Nakamura, M., Imai, Y., Yamahata, S., Umeda, Y.
Published in IEEE journal of solid-state circuits (01.08.1996)
Published in IEEE journal of solid-state circuits (01.08.1996)
Get full text
Journal Article
High-Speed and High-Reliability InP-Based HBTs With a Novel Emitter
Kashio, N., Kurishima, K., Fukai, Y.K., Ida, M., Yamahata, S.
Published in IEEE transactions on electron devices (01.02.2010)
Published in IEEE transactions on electron devices (01.02.2010)
Get full text
Journal Article
A 13-Gb/s pin-PD/decision circuit using InP-InGaAs double-heterojunction bipolar transistors
Yoneyama, M., Sano, E., Yamahata, S., Matsuoka, Y.
Published in IEEE photonics technology letters (01.02.1996)
Published in IEEE photonics technology letters (01.02.1996)
Get full text
Journal Article
A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector
Nosaka, H., Sano, E., Ishii, K., Ida, M., Kurishima, K., Yamahata, S., Shibata, T.
Published in 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) (2003)
Published in 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) (2003)
Get full text
Conference Proceeding
A monolithically integrated photoreceiver realized by InP/InGaAs double-heterostructure bipolar transistor technologies for optical/microwave interaction systems
Kamitsuna, H., Matsuoka, Y., Yamahata, S., Kurishima, K.
Published in GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995 (1995)
Published in GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995 (1995)
Get full text
Conference Proceeding
Low-power 50 Gbit/s InP HBT 1:4 demultiplexer IC with multiphase clock architecture
Sano, K., Hirata, M., Murata, K., Yamahata, S., Ida, M., Kurishima, K., Enoki, T., Sugahara, H.
Published in Electronics letters (04.09.2003)
Published in Electronics letters (04.09.2003)
Get full text
Journal Article