Design theory and fabrication process integration of 65nm and 32nm Node Si vertical dual carrier field effect transistor CPU for parallel arrays of computers
Shen, S.G., Xia, P.S., Zhang, L.B., Yang, Y.H., Li, G.H., Yang, R., Huang, D.H., Huang, C.
Published in 2007 7th International Conference on ASIC (01.10.2007)
Published in 2007 7th International Conference on ASIC (01.10.2007)
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