A two-port SRAM using a single-port cell array with a self-timed write-after-read control scheme to save 47% area & 63% standby power
Fujun Bai, Baoyu Xiong, Xiaofei Xue, Weizhe Song, Wu Baofeng, Ni Fu, Bing Yu, Huifu Duan, Xiaowei Han, Minzoni, Alessandro, Qiwei Ren
Published in 2017 IEEE 12th International Conference on ASIC (ASICON) (01.10.2017)
Published in 2017 IEEE 12th International Conference on ASIC (ASICON) (01.10.2017)
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Conference Proceeding
Robust and low power register file in 65 nm technology
Zhang, Xingxing, Li, Yi, Xiong, Baoyu, Han, Jun, Zhang, Yuejun, Dong, Fangyuan, Zhang, Zhang, Yu, Zhiyi, Cheng, Xu, Zeng, Xiaoyang
Published in Journal of semiconductors (01.03.2012)
Published in Journal of semiconductors (01.03.2012)
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Journal Article
A control scheme for a 65nm 32×32b 4-read 2-write register file
Jun Han, Xingxing Zhang, Baoyu Xiong, Zhiyi Yu, Xiaoyang Zeng
Published in 2011 9th IEEE International Conference on ASIC (01.10.2011)
Published in 2011 9th IEEE International Conference on ASIC (01.10.2011)
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Conference Proceeding
Design of a single-ended cell based 65nm 32 × 32b 4R2W register file
Baoyu Xiong, Xingxing Zhang, Jun Han, Zhiyi Yu, Xiaoyang Zeng
Published in 2011 9th IEEE International Conference on ASIC (01.10.2011)
Published in 2011 9th IEEE International Conference on ASIC (01.10.2011)
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Conference Proceeding