Intelligent Methods for Test and Reliability
Amrouch, H., Anders, J., Becker, S., Betka, M., Bleher, G., Domanski, P., Elhamawy, N., Ertl, T., Gatzastras, A., Genssler, P., Hasler, S., Heinrich, M., van Hoorn, A., Jafarzadeh, H., Kallfass, I., Klemme, F., Koch, S., Kusters, R., Lalama, A., Latty, R., Liao, Y., Lylina, N., Haghi, Z. Najafi, Pfluger, D., Polian, I., Rivoir, J., Sauer, M., Schwachhofer, D., Templin, S., Volmer, C., Wagner, S., Weiskopf, D., Wunderlich, H.-J., Yang, B., Zimmermann, M.
Published in 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) (14.03.2022)
Published in 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) (14.03.2022)
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Conference Proceeding
Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch
Asada, K., Wen, X., Holst, S., Miyase, K., Kajihara, S., Kochte, M. A., Schneider, E., Wunderlich, H.-J, Qian, J.
Published in 2015 IEEE 24th Asian Test Symposium (ATS) (01.11.2015)
Published in 2015 IEEE 24th Asian Test Symposium (ATS) (01.11.2015)
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Conference Proceeding
Journal Article
X-masking during logic BIST and its impact on defect coverage
Yuyi Tang, Wunderlich, H.-J., Piet Engelke, Polian, I., Becker, B., Schloffel, J., Hapke, F., Wittke, M.
Published in IEEE transactions on very large scale integration (VLSI) systems (01.02.2006)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.02.2006)
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Journal Article
A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems
Tran, D. A., Virazel, A., Bosio, A., Dilillo, L., Girard, P., Pravossoudovich, S., Wunderlich, H.–J.
Published in Journal of electronic testing (01.08.2014)
Published in Journal of electronic testing (01.08.2014)
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Journal Article
GUARD: GUAranteed reliability in dynamically reconfigurable systems
Hongyan Zhang, Kochte, Michael A., Imhof, Michael E., Bauer, Lars, Wunderlich, H-J, Henkel, Jorg
Published in 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) (01.06.2014)
Published in 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) (01.06.2014)
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Conference Proceeding
Deterministic logic BIST for transition fault testing
GHERMAN, V, WUNDERLICH, H.-J, SCHLOEFFEL, J, GARBERS, M
Published in IET computers & digital techniques (01.05.2007)
Published in IET computers & digital techniques (01.05.2007)
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Conference Proceeding
Journal Article
Efficient online and offline testing of embedded DRAMs
Hellebrand, S., Wunderlich, H.-J., Ivaniuk, A.A., Klimets, Y.V., Yarmolik, V.N.
Published in IEEE transactions on computers (01.07.2002)
Published in IEEE transactions on computers (01.07.2002)
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Journal Article
Application of deterministic logic BIST on industrial circuits
Kiefer, G., Vranken, H., Marinissen, E.J., Wunderlich, H.-J.
Published in Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159) (2000)
Published in Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159) (2000)
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Conference Proceeding
Hardware-optimal test register insertion
Stroele, A.P., Wunderlich, H.-J.
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.06.1998)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.06.1998)
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Journal Article
Multiple distributions for biased random test patterns
Wunderlich, H.-J.
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.06.1990)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.06.1990)
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Journal Article
Minimized power consumption for scan-based BIST
Gerstendorfer, S., Wunderlich, H.-J.
Published in International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) (1999)
Published in International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) (1999)
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Conference Proceeding
The pseudoexhaustive test of sequential circuits
Wunderlich, H.-J., Hellebrand, S.
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.01.1992)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.01.1992)
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Journal Article
A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits
Tran, D. A., Virazel, A., Bosio, A., Dilillo, L., Girard, P., Pravossoudovitch, S., Wunderlich, H.
Published in 2011 Asian Test Symposium (01.11.2011)
Published in 2011 Asian Test Symposium (01.11.2011)
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Conference Proceeding
A pseudo-dynamic comparator for error detection in fault tolerant architectures
Tran, D. A., Virazel, A., Bosio, A., Dilillo, L., Girard, P., Todri, A., Imhof, M. E., Wunderlich, H.
Published in 2012 IEEE 30th VLSI Test Symposium (VTS) (01.04.2012)
Published in 2012 IEEE 30th VLSI Test Symposium (VTS) (01.04.2012)
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Conference Proceeding
Optimized synthesis techniques for testable sequential circuits
Eschermann, B., Wunderlich, H.-J.
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.03.1992)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.03.1992)
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Journal Article
Parity prediction synthesis for nano-electronic gate designs
Tran, D A, Virazel, A, Bosio, A, Dilillo, L, Girard, P, Pravossoudovitch, S, Wunderlich, H
Published in 2010 IEEE International Test Conference (01.11.2010)
Published in 2010 IEEE International Test Conference (01.11.2010)
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Conference Proceeding
Self-adjusting output data compression: An efficient BIST technique for RAMs
Yarmolik, V.N., Hellebrand, S., Wunderlich, H.-J.
Published in Proceedings Design, Automation and Test in Europe (1998)
Published in Proceedings Design, Automation and Test in Europe (1998)
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Conference Proceeding
Error detecting refreshment for embedded DRAMs
Hellebrand, S., Wunderlich, H.-J., Ivaniuk, A., Klimets, Y., Yarmolik, V.N.
Published in Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) (1999)
Published in Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) (1999)
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Conference Proceeding