23.3 A highly integrated smartphone SoC featuring a 2.5GHz octa-core CPU with advanced high-performance and low-power techniques
Mair, Hugh, Gammie, Gordon, Wang, Alice, Gururajarao, Sumanth, Lin, Ichiro, HsinChen Chen, Wuan Kuo, Rajagopalan, Anand, Wei-Zheng Ge, Lagerquist, Rolf, Rahman, Syed, Chung, C. J., Wang, Simon, Lee-Kee Wong, Yi-Chang Zhuang, Li, Kent, Jidong Wang, Minh Chau, Yijing Liu, Dia, Daniel, Peng, Mark, Uming Ko
Published in 2015 IEEE International Solid State Circuits Conference (ISSCC) (01.02.2015)
Published in 2015 IEEE International Solid State Circuits Conference (ISSCC) (01.02.2015)
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Conference Proceeding
Journal Article
3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance
Mair, Hugh, Lin, Gordon, Thippana, Achuta, Li, Kent, Rahman, Manzur, Kuo, Wuan, Yen, David, Zhuang, Yi-Chang, Fu, Ue, Wang, Hung-Wei, Peng, Mark, Wang, Ericbill, Wu, Cheng-Yuh, Dosluoglu, Taner, Gelman, Anatoly, Dia, Daniel, Gurumurthy, Girishankar, Hsieh, Tony, Lin, W.X., Tzeng, Ray, Wu, Jengding, Wang, C.H., Wang, Alice, Ko, Uming, Kao, Ping, Tsai, Yuwen, Gururajarao, Sumanth, Lagerquist, Rolf, Son, Jin, Gammie, Gordon
Published in 2017 IEEE International Solid-State Circuits Conference (ISSCC) (01.02.2017)
Published in 2017 IEEE International Solid-State Circuits Conference (ISSCC) (01.02.2017)
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Conference Proceeding
4.3 A 20nm 2.5GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance
Mair, Hugh T., Gammie, Gordon, Wang, Alice, Lagerquist, Rolf, Chung, C. J., Gururajarao, Sumanth, Kao, Ping, Rajagopalan, Anand, Saha, Anirban, Jain, Amit, Wang, Ericbill, Ouyang, Shichin, Huajun Wen, Thippana, Achuta, HsinChen Chen, Rahman, Syed, Chau, Minh, Varma, Anshul, Flachs, Brian, Peng, Mark, Tsai, Alfred, Lin, Vincent, Ue Fu, Wuan Kuo, Lee-Kee Yong, Clavin Peng, Leo Shieh, Jengding Wu, Uming Ko
Published in 2016 IEEE International Solid-State Circuits Conference (ISSCC) (01.01.2016)
Published in 2016 IEEE International Solid-State Circuits Conference (ISSCC) (01.01.2016)
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Conference Proceeding
10.3 heterogeneous multi-processing quad-core CPU and dual-GPU design for optimal performance, power, and thermal tradeoffs in a 28nm mobile application processor
Wang, Alice, Tsung-Yao Lin, Shichin Ouyang, Wei-Hung Huang, Jidong Wang, Shu-Hsin Chang, Sheng-Ping Chen, Chun-Hsiung Hu, Tai, Jim C., Koan-Sin Tan, Meng-Nan Tsou, Ming-Hsien Lee, Gammie, Gordon, Chi-Wei Yang, Chih-Chieh Yang, Yeh-Chi Chou, Shih-Hung Lin, Wuan Kuo, Chi-Jui Chung, Lee-Kee Yong, Chia-Wei Wang, Kin Hooi Dia, Cheng-Hsing Chien, You-Ming Tsao, Singh, Nitin Kumar, Lagerquist, Rolf, Chih-Cheng Chen, Uming Ko
Published in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (01.02.2014)
Published in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (01.02.2014)
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