8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology
KANG, Uksong, CHUNG, Hoe-Ju, LEE, Jae-Wook, JOO, Han-Sung, KIM, Woo-Seop, DONG HYEON JANG, NAM SEOG KIM, CHOI, Jung-Hwan, CHUNG, Tae-Gyeong, YOO, Jei-Hwan, JOO SUN CHOI, KIM, Changhyun, HEO, Seongmoo, JUN, Young-Hyun, PARK, Duk-Ha, LEE, Hoon, JIN HO KIM, AHN, Soon-Hong, CHA, Soo-Ho, AHN, Jaesung, KWON, Dukmin
Published in IEEE journal of solid-state circuits (01.01.2010)
Published in IEEE journal of solid-state circuits (01.01.2010)
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A 31 ns Random Cycle VCAT-Based 4F ^ DRAM With Manufacturability and Enhanced Cell Efficiency
Song, Ki-Whan, Kim, Jin-Young, Yoon, Jae-Man, Kim, Sua, Kim, Huijung, Chung, Hyun-Woo, Kim, Hyungi, Kim, Kanguk, Park, Hwan-Wook, Kang, Hyun Chul, Tak, Nam-Kyun, Park, Dukha, Kim, Woo-Seop, Lee, Yeong-Taek, Oh, Yong Chul, Jin, Gyo-Young, Yoo, Jeihwan, Park, Donggun, Oh, Kyungseok, Kim, Changhyun, Jun, Young-Hyun
Published in IEEE journal of solid-state circuits (01.04.2010)
Published in IEEE journal of solid-state circuits (01.04.2010)
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BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel
JANG, Young-Chan, CHUNG, Hoeju, LEE, Yun-Sang, KIM, Woo-Seop, LEE, Jung-Bae, YOO, Jeihwan, KIM, Changhyun, CHOI, Youngdon, PARK, Hwanwook, KIM, Jaekwan, LIM, Soouk, SUNWOO, Jung, PARK, Moon-Sook, KIM, Hyung-Seuk, KIM, Sang-Yun
Published in IEEE journal of solid-state circuits (01.11.2009)
Published in IEEE journal of solid-state circuits (01.11.2009)
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A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter
KIM, Kyu-Hyoun, SOHN, Young-Soo, KIM, Chan-Kyoung, PARK, Moonsook, LEE, Dong-Jin, KIM, Woo-Seop, KIM, Changhyun
Published in IEEE journal of solid-state circuits (01.01.2006)
Published in IEEE journal of solid-state circuits (01.01.2006)
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A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling
KIM, Jin-Hyun, KIM, Sua, KIM, Woo-Seop, CHOI, Jung-Hwan, HWANG, Hong-Sun, KIM, Changhyun, KIM, Suki
Published in IEEE journal of solid-state circuits (01.01.2005)
Published in IEEE journal of solid-state circuits (01.01.2005)
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A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems
Kennedy, J., Mooney, R., Ellis, R., Jaussi, J., Borkar, S., Jung-Hwan Choi, Jae-Kwan Kim, Chan-Kyong Kim, Woo-Seop Kim, Chang-Hyun Kim, Soo-In Cho, Loeffler, S., Hoffmann, J., Hokenmaier, W., Houghton, R., Vogelsang, T.
Published in IEEE journal of solid-state circuits (01.01.2005)
Published in IEEE journal of solid-state circuits (01.01.2005)
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An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme
Kyu-hyoun Kim, Hoe-Ju Chung, Woo-Seop Kim, Moonsook Park, Jang, Y.-C., Jin-Young Kim, Hwan-Wook Park, Uksong Kang, Coteus, P.W., Joo Sun Choi, Changhyun Kim
Published in IEEE journal of solid-state circuits (01.01.2007)
Published in IEEE journal of solid-state circuits (01.01.2007)
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8Gb 3D DDR3 DRAM using through-silicon-via technology
Uksong Kang, Hoe-Ju Chung, Seongmoo Heo, Soon-Hong Ahn, Hoon Lee, Soo-Ho Cha, Jaesung Ahn, DukMin Kwon, Jin Ho Kim, Jae-Wook Lee, Han-Sung Joo, Woo-Seop Kim, Hyun-Kyung Kim, Eun-Mi Lee, So-Ra Kim, Keum-Hee Ma, Dong-Hyun Jang, Nam-Seog Kim, Man-Sik Choi, Sae-Jang Oh, Jung-Bae Lee, Tae-Kyung Jung, Jei-Hwan Yoo, Changhyun Kim
Published in 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers (01.02.2009)
Published in 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers (01.02.2009)
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A 4-Gbps/pin transceiver with a multi-level simultaneous bi-directional scheme for serial link applications
Kim, Woo-Seop, Kim, Jin-Hyun, Kim, Chang-Hyun, Kim, Suki
Published in Current applied physics (01.02.2004)
Published in Current applied physics (01.02.2004)
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A control protocol architecture based on LonTalk protocol for power line data communications
KIM, Woo-Seop, KIM, Lok-Won, LEE, Chang-Eun, MOON, Kyeong-Deok, SUKI KIM
Published in 2002 Digest of Technical Papers. International Conference on Consumer Electronics (IEEE Cat. No.02CH37300) (2002)
Published in 2002 Digest of Technical Papers. International Conference on Consumer Electronics (IEEE Cat. No.02CH37300) (2002)
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A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW
Seung-Jun Bae, Young-Soo Sohn, Tae-Young Oh, Si-Hong Kim, Yun-Seok Yang, Dae-Hyun Kim, Sang-Hyup Kwak, Ho-Seok Seol, Chang-Ho Shin, Min-Sang Park, Gong-Heom Han, Byeong-Cheol Kim, Yong-Ki Cho, Hye-Ran Kim, Su-Yeon Doo, Young-Sik Kim, Dong-Seok Kang, Young-Ryeol Choi, Sam-Young Bang, Sun-Young Park, Yong-Jae Shin, Gil-Shin Moon, Cheol-Goo Park, Woo-Seop Kim, Hyang-Ja Yang, Jeong-Don Lim, Kwang-Il Park, Joo Sun Choi, Young-Hyun Jun
Published in 2011 IEEE International Solid-State Circuits Conference (01.02.2011)
Published in 2011 IEEE International Solid-State Circuits Conference (01.02.2011)
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Channel BER Measurement for a 5.8Gb/s/pin unidirectional differential I/O for DRAM application
Hoeju Chung, Youngchan Jang, Youngdon Choi, Hwanwook Park, Jaekwan Kim, Soouk Lim, Jung Sunwoo, Moonsook Park, Hyungwsuk Kim, Sang-Yun Kim, Hyun-Kyung Kim, Su-Jin Chung, Eun-Mi Lee, Youngju Kim, Yun-Sang Lee, Woo-Seop Kim, Jung-Bae Lee, Changhyun Kim
Published in 2008 IEEE Asian Solid-State Circuits Conference (01.11.2008)
Published in 2008 IEEE Asian Solid-State Circuits Conference (01.11.2008)
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Conference Proceeding
BER Simulator Development for Link Compliance Analysis
Kang, Hyun-Chul, Kim, Woo-Seop, Lee, Jae-Wook, Jang, Young-Chan, Park, Hwan-Wook, Kim, Jong-Hoon, Lee, Jung-Bae, Kim, Chang-Hyun
Published in Journal of semiconductor technology and science (30.06.2008)
Published in Journal of semiconductor technology and science (30.06.2008)
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A 6-Gbps/pin Half-Duplex LVDS I/O for High-Speed Mobile DRAM
Sua Kim, Bae-Sun Kong, Chil-gi Lee, Jin-Hyun Kim, Woo-Seop Kim, Young-Hyun Jun, Changhyun Kim
Published in 2005 IEEE Asian Solid-State Circuits Conference (01.11.2005)
Published in 2005 IEEE Asian Solid-State Circuits Conference (01.11.2005)
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Conference Proceeding
55 nm capacitor-less 1T DRAM cell transistor with non-overlap structure
Ki-Whan Song, Hoon Jeong, Jae-Wook Lee, Sung In Hong, Nam-Kyun Tak, Young-Tae Kim, Yong Lack Choi, Han Sung Joo, Sung Hwan Kim, Ho Ju Song, Yong Chul Oh, Woo-Seop Kim, Yeong-Taek Lee, Kyungseok Oh, Changhyun Kim
Published in 2008 IEEE International Electron Devices Meeting (01.12.2008)
Published in 2008 IEEE International Electron Devices Meeting (01.12.2008)
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Conference Proceeding
Noise immunity improvement in the RESET signal of DDR3 SDRAM memory module
Seung Mo Jung, Jong Hyun Seok, Ho Jin Yoo, Do Hyung Kim, You Keun Han, Woo Seop Kim, Joo Sun Choi, Jun Dong Cho
Published in 2013 IEEE International SOC Conference (01.09.2013)
Published in 2013 IEEE International SOC Conference (01.09.2013)
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Conference Proceeding
A 2Gb/s point-to-point heterogeneous voltage capable DRAM interface for capacity-scalable memory subsystems
Kennedy, J., Ellis, R., Jaussi, J., Mooney, R., Borkar, S., Jung-Hwan Choi, Jae-Kwan Kim, Chan-Kyong Kim, Woo-Seop Kim, Chang-Hyun Kim, Soo-In Cho, Loeffler, S., Hoffmann, J., Hokenmaier, W., Houghton, R., Vogelsang, T.
Published in 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) (2004)
Published in 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) (2004)
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Conference Proceeding
Self-calibrating transceiver for source synchronous clocking system with on-chip TDR and swing level control scheme
Jang, Young-Chan, Park, Joon-Young, Shin, Sungcheol, Choi, Hundae, Lee, Kyongsu, Woo, Byungsuk, Park, Hwanwook, Kim, Woo-Seop, Choi, Youngdon, Kim, Jaekwan, Kim, Hyun-Kyung, Kim, Jayoung, Lim, Suyoun, Chung, Su-Jin, Kim, Sora, Yoo, Jeihwan, Kim, Changhyun
Published in 2009 Symposium on VLSI Circuits (01.06.2009)
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Published in 2009 Symposium on VLSI Circuits (01.06.2009)
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