Search Results - "Walter, Dennis" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology

Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology

by Hoppner, Sebastian, Eisenreich, Holger, Walter, Dennis, Scharfe, Andre, Oefelein, Alexander, Schraut, Florian, Schreiter, Jorg, Riedel, Thorsten, Bauer, Heiner, Niebsch, Robert, Scherzer, Stephan, Hocker, Thomas, Scholze, Stefan, Henker, Stephan, Nossmann, Matthias, Hensel, Ulrich, Prengel, Helmut
Published in IEEE transactions on circuits and systems. II, Express briefs (01.10.2020)

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Journal Article

Handbook of Latent Semantic Analysis

Handbook of Latent Semantic Analysis

by Landauer, Thomas K., Ed, McNamara, Danielle S., Ed, Dennis, Simon, Ed, Kintsch, Walter, Ed
Published in Routledge, Taylor & Francis Group (15.02.2007)

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Book

SYSTEM FOR SENSING MOVING DIRECTION OF RFID TAG

SYSTEM FOR SENSING MOVING DIRECTION OF RFID TAG

by WALTER DENNIS BURNSIDE, TSAI WEI-FENG
Year of Publication 27.09.2023

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Patent

Perforated liner

Perforated liner

by WALTER DENNIS
Year of Publication 22.03.2017

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Patent

Oxygen measurements in biology and medicine

Oxygen measurements in biology and medicine

by Payne, J. P. (James Patrick), Hill, D. W. (Dennis Walter)
Year of Publication 1975

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Book

RFID RFID FOLDABLE ANTENNA

RFID RFID FOLDABLE ANTENNA

by BURNSIDE WALTER DENNIS, BURNSIDE JEFFREY J, BURKHOLDER ROBERT J
Year of Publication 29.08.2024

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Patent

A 16-Channel Fully Configurable Neural SoC With 1.52 μW/Ch Signal Acquisition, 2.79 μW/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI

A 16-Channel Fully Configurable Neural SoC With 1.52 μW/Ch Signal Acquisition, 2.79 μW/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI

by Zeinolabedin, Seyed Mohammad Ali, Schuffny, Franz Marcus, George, Richard, Kelber, Florian, Bauer, Heiner, Scholze, Stefan, Hanzsche, Stefan, Stolba, Marco, Dixius, Andreas, Ellguth, Georg, Walter, Dennis, Hoppner, Sebastian, Mayr, Christian
Published in IEEE transactions on biomedical circuits and systems (01.02.2022)

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Journal Article

A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology

A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology

by Hoppner, Sebastian, Haenzsche, Stefan, Ellguth, Georg, Walter, Dennis, Eisenreich, Holger, Schuffny, Rene
Published in IEEE transactions on circuits and systems. II, Express briefs (01.11.2013)

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Journal Article

Hardware Implementation of an OPC UA Server for Industrial Field Devices

Hardware Implementation of an OPC UA Server for Industrial Field Devices

by Bauer, Heiner, Hoppner, Sebastian, Iatrou, Chris, Charania, Zohra, Hartmann, Stephan, Rehman, Saif Ur, Dixius, Andreas, Ellguth, Georg, Walter, Dennis, Uhlig, Johannes, Neumarker, Felix, Berthel, Marc, Stolba, Marco, Kelber, Florian, Urbas, Leon, Mayr, Christian
Published in IEEE transactions on very large scale integration (VLSI) systems (01.11.2021)

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Journal Article

Exploiting transistor-level reconfiguration to optimize combinational circuits

Exploiting transistor-level reconfiguration to optimize combinational circuits

by Raitza, Michael, Kumar, Akash, Volp, Marcus, Walter, Dennis, Trommer, Jens, Mikolajick, Thomas, Weber, Walter M.
Published in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 (01.03.2017)

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Conference Proceeding

$A 16-Channel Fully Configurable Neural SoC With 1.52 \muW/Ch Signal Acquisition, 2.79 \muW/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI$

A 16-Channel Fully Configurable Neural SoC With 1.52 \muW/Ch Signal Acquisition, 2.79 \muW/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI

by Zeinolabedin, Seyed Mohammad Ali, Schuffny, Franz Marcus, George, Richard, Kelber, Florian, Bauer, Heiner, Scholze, Stefan, Hanzsche, Stefan, Stolba, Marco, Dixius, Andreas, Ellguth, Georg, Walter, Dennis, Hoppner, Sebastian, Mayr, Christian
Published in IEEE transactions on biomedical circuits and systems (01.02.2022)

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Journal Article

A 16-Channel Fully Configurable Neural SoC With 1.52 [Formula Omitted]W/Ch Signal Acquisition, 2.79 [Formula Omitted]W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI

A 16-Channel Fully Configurable Neural SoC With 1.52 [Formula Omitted]W/Ch Signal Acquisition, 2.79 [Formula Omitted]W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI

by Seyed Mohammad Ali Zeinolabedin, Franz Marcus Schuffny, George, Richard, Kelber, Florian, Bauer, Heiner, Scholze, Stefan, Hanzsche, Stefan, Stolba, Marco, Dixius, Andreas, Ellguth, Georg, Walter, Dennis, Hoppner, Sebastian, Mayr, Christian
Published in IEEE transactions on biomedical circuits and systems (01.01.2022)

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Journal Article

An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS

An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS

by Hoppner, Sebastian, Walter, Dennis, Hocker, Thomas, Henker, Stephan, Hanzsche, Stefan, Sausner, Daniel, Ellguth, Georg, Schlussler, Jens-Uwe, Eisenreich, Holger, Schuffny, Rene
Published in IEEE journal of solid-state circuits (01.03.2015)

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Journal Article

A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs

A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs

by Rai, Shubham, Rupani, Ansh, Walter, Dennis, Raitza, Michael, Heinzig, Andre, Baldauf, Tim, Trommer, Jens, Mayr, Christian, Weber, Walter M., Kumar, Akash
Published in 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) (01.03.2018)

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Conference Proceeding

Guaranteeing functional safety: design for provability and computer-aided verification

Guaranteeing functional safety: design for provability and computer-aided verification

by Täubig, Holger, Frese, Udo, Hertzberg, Christoph, Lüth, Christoph, Mohr, Stefan, Vorobev, Elena, Walter, Dennis
Published in Autonomous robots (01.04.2012)

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Journal Article

PRESSURE BALANCED VALVE

PRESSURE BALANCED VALVE

by ROBERTSON WALTER DENNIS III
Year of Publication 10.03.2014

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Patent

A 12-ADC 25-Core Smart MPSoC Using ABB in 22FDX for 77GHz MIMO Radars at 52.6mW Average Power

A 12-ADC 25-Core Smart MPSoC Using ABB in 22FDX for 77GHz MIMO Radars at 52.6mW Average Power

by Gonzalez, Hector A., Vogginger, Bernhard, Liu, Chen, Stolba, Marco, Kelber, Florian, Bauer, Heiner, Hanzsche, Stefan, Scholze, Stefan, Berthel, Marc, Rosmeisl, Tim, Guo, Liyuan, Walter, Dennis, Das, Piash, Khan, Khaleelulla, Schubert, Tilo, Hoppner, Sebastian, Mayr, Christian
Published in 2023 IEEE Custom Integrated Circuits Conference (CICC) (01.04.2023)

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Conference Proceeding

How to Achieve World-Leading Energy Efficiency using 22FDX with Adaptive Body Biasing on an Arm Cortex-M4 IoT SoC

How to Achieve World-Leading Energy Efficiency using 22FDX with Adaptive Body Biasing on an Arm Cortex-M4 IoT SoC

by Hoppner, Sebastian, Schreiter, Jorg, Niebsch, Robert, Scherzer, Stephan, Hensel, Ulrich, Winkler, Jorg, Orgis, Mario, Eisenreich, Holger, Walter, Dennis, Steeb, Uwe, Clifford Dmello, Andre Scharfe, Sinkwitz, Robert, Bauer, Heiner, Oefelein, Alexander, Schraut, Florian
Published in ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC) (01.09.2019)

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Conference Proceeding

Efficient compensation of delay variations in high-speed network-on-chip data links

Efficient compensation of delay variations in high-speed network-on-chip data links

by Höppner, Sebastian, Walter, Dennis, Eisenreich, Holger, Schüffny, René
Published in 2010 International Symposium on System on Chip (01.09.2010)

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Conference Proceeding

A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology

A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology

by Hoppner, S., Eisenreich, H., Henker, S., Walter, D., Ellguth, G., Schuffny, R.
Published in IEEE transactions on very large scale integration (VLSI) systems (01.03.2013)

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Journal Article

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