METHOD AND APPARATUS FOR USING CACHE MEMORY IN A SYSTEM THAT SUPPORTS A LOW POWER STATE
SOMASEKHAR DINESH, WILKERSON CHRISTOPHER B, ALAMELDEEN ALAA R, LU SHIH LIEN, WU WEI, CHISHTI ZESHAN A
Year of Publication 28.02.2013
Get full text
Year of Publication 28.02.2013
Patent
Ferroelectric memory chiplet in a multi-dimensional packaging
Manipatruni, Sasikanth, Wilkerson, Christopher B, Dokania, Rajeev Kumar, Mathuriya, Amrita, Olaosebikan, Debo
Year of Publication 03.09.2024
Get full text
Year of Publication 03.09.2024
Patent
Method and apparatus for managing power in a multi-dimensional packaging
Manipatruni, Sasikanth, Wilkerson, Christopher B, Dokania, Rajeev Kumar, Mathuriya, Amrita, Olaosebikan, Debo
Year of Publication 25.06.2024
Get full text
Year of Publication 25.06.2024
Patent
Method for improving memory bandwidth through read and restore decoupling
Manipatruni, Sasikanth, Wilkerson, Christopher B, Dokania, Rajeev Kumar, Mathuriya, Amrita
Year of Publication 28.06.2022
Get full text
Year of Publication 28.06.2022
Patent
Apparatus for improving memory bandwidth through read and restore decoupling
Manipatruni, Sasikanth, Wilkerson, Christopher B, Dokania, Rajeev Kumar, Mathuriya, Amrita
Year of Publication 28.06.2022
Get full text
Year of Publication 28.06.2022
Patent
Method and apparatus to process an instruction for a distributed logic having tightly coupled accelerator core and processor core in a multi-dimensional packaging
Manipatruni, Sasikanth, Wilkerson, Christopher B, Dokania, Rajeev Kumar, Mathuriya, Amrita, Olaosebikan, Debo
Year of Publication 13.02.2024
Get full text
Year of Publication 13.02.2024
Patent