Search Results - "WIK THOMAS R" :: K.UTB vyhledávací portál

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Conditioning logic technology

by Wik, Thomas R
Year of Publication 07.07.2009

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Conditioning logic technology

by WIK THOMAS R
Year of Publication 07.07.2009

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Patent

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Memory system using multiple storage mechanisms to enable storage and retrieval of more than two states in a memory cell

by WIK; THOMAS R
Year of Publication 24.10.2000

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MEMORY SYSTEM USING MULTIVALUED STORAGE MECHANISM BY WHICH THREE OR MORE STATES ARE STORABLE ARE READABLE IN A MEMORY CELL

by WIK THOMAS R
Year of Publication 09.03.1999

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Memory system using multiple storage mechanisms to enable storage and retrieval of more than two states in a memory cell

by WIK; THOMAS R
Year of Publication 24.11.1998

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Integrated circuit memory having column redundancy

by Agrawal, Ghasi, Wik, Thomas R
Year of Publication 14.01.2003

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Integrated circuit memory having column redundancy

by AGRAWAL GHASI, WIK THOMAS R
Year of Publication 14.01.2003

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Memory circuit including write control unit wherein subthreshold leakage may be reduced

by WIK; THOMAS R, ARYANI; SHAHRYAR
Year of Publication 18.08.1998

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Way to compensate the effect of coupling between bitlines in a multi-port memories

by Wik, Thomas R, Agrawal, Ghasi R
Year of Publication 09.04.2002

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Way to compensate the effect of coupling between bitlines in a multi-port memories

by AGRAWAL GHASI R, WIK THOMAS R
Year of Publication 09.04.2002

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Multi-port semiconductor memory and compiler having capacitance compensation

by AGRAWAL GHASI R, WIK THOMAS R
Year of Publication 15.05.2001

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Method of testing memory operations employing self-repair circuitry and permanently disabling memory locations

by IRRINKI; V. SWAMY, WIK; THOMAS R
Year of Publication 16.11.1999

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Method of testing memory refresh operations wherein subthreshold leakage current may be set to near worst-case conditions

by TRIEU; THIEN, PHAN; TUAN, WIK; THOMAS R
Year of Publication 11.05.1999

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METHOD FOR TESTING MEMORY OPERATION IN WHICH SELF REPAIR CIRCUIT IS USED AND MEMORY POSITION IS DISABLED FOREVER

by IRRINKI V SWAMY, WIK THOMAS R
Year of Publication 30.04.1999

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METHOD FOR TESTING REFRESH OPERATION OF MEMORY WHOSE SUBTHRESHOLD LEAKAGE CURRENT MAY BE SET AT WORST CONDITION

by CHUAN FAN, CHEN TOREU, WIK THOMAS R
Year of Publication 22.01.1999

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Integrated circuit margin stress test system

by NGUYEN HIEU D, LECLAIR KEVIN R, TRAN DUYTAN K, LE CHUONG T, WIK THOMAS R, BLIGH KEVIN O
Year of Publication 28.09.2006

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Method and system which permits logic signal routing over on-chip memories

by REDDING; KEN, PASSOW; ROBIN, BUER; MYRON, WIK; THOMAS R
Year of Publication 25.01.2000

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Memory cell capable of storing more than two logic states by using different via resistances

by KAPOOR; ASHOK, LEUNG; RAYMOND T, IRRINKI; V. SWAMY, WIK; THOMAS R, OWENS; ALEX
Year of Publication 09.11.1999

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Memory system including an on-chip temperature sensor for regulating the refresh rate of a dram array

by IRRINKI, SWAMY V, WIK, THOMAS R, OWENS, ALEX, KAPOOR, ASHOK, LEUNG, RAYMOND
Year of Publication 14.07.1999

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Memory circuit and method for multivalued logic storage by process variations

by KAPOOR; ASHOK, LEUNG; RAYMOND T, OWENS; ALEX, WIK; THOMAS R, IRRINKI; V. SWAMY
Year of Publication 02.02.1999

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