Search Results - "WEILAND LARG" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells

by Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 09.10.2018

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Patent

Test vehicle with zig-zag structures

Test vehicle with zig-zag structures

by Hess, Christopher, Weiland, Larg
Year of Publication 30.01.2003

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Patent

Integrated circuit containing DOEs of GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells

Integrated circuit containing DOEs of GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells

by Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 29.05.2018

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Patent

Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of GATECNT-GATE via opens

Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of GATECNT-GATE via opens

by Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 24.04.2018

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Patent

Integrated circuit including NCEM-enabled, side-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Integrated circuit including NCEM-enabled, side-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

by Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 17.04.2018

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Patent

Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

by Cheng Jeremy, De Indranil, Eisenmann Hans, Matsuhashi Hideki, Yokoyama Nobuharu, Lin Sheng-Che, Vallishayee Rakesh, Doong Kelvin, Liao Marci, Strojwas Andrzej, Ciplickas Dennis, Brozek Tomasz, Hess Christopher, Fiscus Timothy, Taylor Carl, Weiland Larg, Lee Sherry, Rovner Vyacheslav, Lam Stephen, Haigh Jonathan, O'Sullivan Conor, Michaels Kimon, Comensoli Simone, Strojwas Marcin, Rauscher Markus, Kibarian John
Year of Publication 27.03.2018

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Patent

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-Enabled fill cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-Enabled fill cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells

by Cheng Jeremy, De Indranil, Eisenmann Hans, Matsuhashi Hideki, Yokoyama Nobuharu, Lin Sheng-Che, Vallishayee Rakesh, Doong Kelvin, Liao Marci, Strojwas Andrzej, Ciplickas Dennis, Brozek Tomasz, Hess Christopher, Fiscus Timothy, Taylor Carl, Weiland Larg, Lee Sherry, Rovner Vyacheslav, Lam Stephen, Haigh Jonathan, O'Sullivan Conor, Michaels Kimon, Comensoli Simone, Strojwas Marcin, Rauscher Markus, Kibarian John
Year of Publication 27.03.2018

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Patent

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells

by Cheng Jeremy, De Indranil, Eisenmann Hans, Matsuhashi Hideki, Yokoyama Nobuharu, Lin Sheng-Che, Vallishayee Rakesh, Doong Kelvin, Liao Marci, Strojwas Andrzej, Ciplickas Dennis, Brozek Tomasz, Hess Christopher, Fiscus Timothy, Taylor Carl, Weiland Larg, Lee Sherry, Rovner Vyacheslav, Lam Stephen, Haigh Jonathan, O'Sullivan Conor, Michaels Kimon, Comensoli Simone, Strojwas Marcin, Rauscher Markus, Kibarian John
Year of Publication 20.03.2018

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Patent

Integrated circuit including NCEM-enabled, snake-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Integrated circuit including NCEM-enabled, snake-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

by Cheng Jeremy, De Indranil, Eisenmann Hans, Matsuhashi Hideki, Yokoyama Nobuharu, Lin Sheng-Che, Vallishayee Rakesh, Doong Kelvin, Liao Marci, Strojwas Andrzej, Ciplickas Dennis, Brozek Tomasz, Hess Christopher, Fiscus Timothy, Taylor Carl, Weiland Larg, Lee Sherry, Rovner Vyacheslav, Lam Stephen, Haigh Jonathan, O'Sullivan Conor, Michaels Kimon, Comensoli Simone, Strojwas Marcin, Rauscher Markus, Kibarian John
Year of Publication 20.03.2018

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Patent

Integrated circuit including NCEM-enabled, diagonal gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Integrated circuit including NCEM-enabled, diagonal gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

by Cheng Jeremy, De Indranil, Eisenmann Hans, Matsuhashi Hideki, Yokoyama Nobuharu, Lin Sheng-Che, Vallishayee Rakesh, Doong Kelvin, Liao Marci, Strojwas Andrzej, Ciplickas Dennis, Brozek Tomasz, Hess Christopher, Fiscus Timothy, Taylor Carl, Weiland Larg, Lee Sherry, Rovner Vyacheslav, Lam Stephen, Haigh Jonathan, O'Sullivan Conor, Michaels Kimon, Comensoli Simone, Strojwas Marcin, Rauscher Markus, Kibarian John
Year of Publication 06.03.2018

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Patent

Process for making and using mesh-style NCEM pads

Process for making and using mesh-style NCEM pads

by Cheng Jeremy, De Indranil, Eisenmann Hans, Matsuhashi Hideki, Yokoyama Nobuharu, Lin Sheng-Che, Vallishayee Rakesh, Doong Kelvin, Liao Marci, Strojwas Andrzej, Ciplickas Dennis, Brozek Tomasz, Hess Christopher, Fiscus Timothy, Taylor Carl, Weiland Larg, Lee Sherry, Rovner Vyacheslav, Lam Stephen, Haigh Jonathan, O'Sullivan Conor, Michaels Kimon, Comensoli Simone, Strojwas Marcin, Rauscher Markus, Kibarian John
Year of Publication 06.03.2018

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Patent

Integrated circuit including NCEM-enabled, via-open/resistance-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gate

Integrated circuit including NCEM-enabled, via-open/resistance-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gate

by Cheng Jeremy, De Indranil, Eisenmann Hans, Matsuhashi Hideki, Yokoyama Nobuharu, Lin Sheng-Che, Vallishayee Rakesh, Doong Kelvin, Liao Marci, Strojwas Andrzej, Ciplickas Dennis, Brozek Tomasz, Hess Christopher, Fiscus Timothy, Taylor Carl, Weiland Larg, Lee Sherry, Rovner Vyacheslav, Lam Stephen, Haigh Jonathan, O'Sullivan Conor, Michaels Kimon, Comensoli Simone, Strojwas Marcin, Rauscher Markus, Kibarian John
Year of Publication 06.03.2018

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Patent

Integrated circuit including NCEM-enabled, corner gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Integrated circuit including NCEM-enabled, corner gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

by Cheng Jeremy, De Indranil, Eisenmann Hans, Matsuhashi Hideki, Yokoyama Nobuharu, Lin Sheng-Che, Vallishayee Rakesh, Doong Kelvin, Liao Marci, Strojwas Andrzej, Ciplickas Dennis, Brozek Tomasz, Hess Christopher, Fiscus Timothy, Taylor Carl, Weiland Larg, Lee Sherry, Rovner Vyacheslav, Lam Stephen, Haigh Jonathan, O'Sullivan Conor, Michaels Kimon, Comensoli Simone, Strojwas Marcin, Rauscher Markus, Kibarian John
Year of Publication 06.03.2018

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Patent

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells

by Cheng Jeremy, De Indranil, Eisenmann Hans, Matsuhashi Hideki, Yokoyama Nobuharu, Lin Sheng-Che, Vallishayee Rakesh, Doong Kelvin, Liao Marci, Strojwas Andrzej, Ciplickas Dennis, Brozek Tomasz, Hess Christopher, Fiscus Timothy, Taylor Carl, Weiland Larg, Lee Sherry, Rovner Vyacheslav, Lam Stephen, Haigh Jonathan, O'Sullivan Conor, Michaels Kimon, Comensoli Simone, Strojwas Marcin, Rauscher Markus, Kibarian John
Year of Publication 27.02.2018

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Patent

Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of V0 via opens

Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of V0 via opens

by Cheng Jeremy, De Indranil, Eisenmann Hans, Matsuhashi Hideki, Yokoyama Nobuharu, Lin Sheng-Che, Vallishayee Rakesh, Doong Kelvin, Liao Marci, Strojwas Andrzej, Ciplickas Dennis, Brozek Tomasz, Hess Christopher, Fiscus Timothy, Taylor Carl, Weiland Larg, Lee Sherry, Rovner Vyacheslav, Lam Stephen, Haigh Jonathan, O'Sullivan Conor, Michaels Kimon, Comensoli Simone, Strojwas Marcin, Rauscher Markus, Kibarian John
Year of Publication 27.02.2018

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Patent

Process for making an integrated circuit that includes NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Process for making an integrated circuit that includes NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

by Cheng Jeremy, De Indranil, Eisenmann Hans, Matsuhashi Hideki, Yokoyama Nobuharu, Lin Sheng-Che, Vallishayee Rakesh, Doong Kelvin, Liao Marci, Strojwas Andrzej, Ciplickas Dennis, Brozek Tomasz, Hess Christopher, Fiscus Timothy, Taylor Carl, Weiland Larg, Lee Sherry, Rovner Vyacheslav, Lam Stephen, Haigh Jonathan, O'Sullivan Conor, Michaels Kimon, Comensoli Simone, Strojwas Marcin, Rauscher Markus, Kibarian John
Year of Publication 20.02.2018

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Patent

Integrated circuit including NCEM-Enabled, tip-to-tip gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Integrated circuit including NCEM-Enabled, tip-to-tip gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

by Cheng Jeremy, De Indranil, Eisenmann Hans, Matsuhashi Hideki, Yokoyama Nobuharu, Lin Sheng-Che, Vallishayee Rakesh, Doong Kelvin, Liao Marci, Strojwas Andrzej, Ciplickas Dennis, Brozek Tomasz, Hess Christopher, Fiscus Timothy, Taylor Carl, Weiland Larg, Lee Sherry, Rovner Vyacheslav, Lam Stephen, Haigh Jonathan, O'Sullivan Conor, Michaels Kimon, Comensoli Simone, Strojwas Marcin, Rauscher Markus, Kibarian John
Year of Publication 30.01.2018

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Patent

INTEGRATED CIRCUIT CONTAINING DOES OF NCEM-ENABLED FILL CELLS

INTEGRATED CIRCUIT CONTAINING DOES OF NCEM-ENABLED FILL CELLS

by RAUSCHER, Markus, O'SULLIVAN, Conor, WEILAND, Larg, YOKOYAMA, Nobuharu, CIPLICKAS, Dennis, BROZEK, Tomasz, HAIGH, Jonathan, DE, Indranil, VALLISHAYEE, Rakesh, STROJWAS, Marcin, KIBARIAN, John, CHENG, Jeremy, MICHAELS, Kimon, DOONG, Kelvin, EISENMANN, Hans, ROVNER, Vyacheslav, LIN, Sheng-Che, COMENSOLI, Simone, HESS, Christopher, LAM, Stephen, MATSUHASHI, Hideki, LIAO, Marci, STROJWAS, Andrzej, TAYLOR, Carl, FISCUS, Timothy, LEE, Sherry
Year of Publication 18.01.2018

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Patent

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including tip-to-tip short configured fill cells, and the second DOE including chamfer short configured fill cells

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including tip-to-tip short configured fill cells, and the second DOE including chamfer short configured fill cells

by Cheng Jeremy, De Indranil, Eisenmann Hans, Matsuhashi Hideki, Yokoyama Nobuharu, Lin Sheng-Che, Vallishayee Rakesh, Doong Kelvin, Liao Marci, Strojwas Andrzej, Ciplickas Dennis, Brozek Tomasz, Hess Christopher, Fiscus Timothy, Taylor Carl, Weiland Larg, Lee Sherry, Rovner Vyacheslav, Lam Stephen, Haigh Jonathan, O'Sullivan Conor, Michaels Kimon, Comensoli Simone, Strojwas Marcin, Rauscher Markus, Kibarian John
Year of Publication 16.01.2018

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Patent

Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

by Cheng Jeremy, De Indranil, Eisenmann Hans, Matsuhashi Hideki, Yokoyama Nobuharu, Lin Sheng-Che, Vallishayee Rakesh, Doong Kelvin, Liao Marci, Strojwas Andrzej, Ciplickas Dennis, Brozek Tomasz, Hess Christopher, Fiscus Timothy, Taylor Carl, Weiland Larg, Lee Sherry, Rovner Vyacheslav, Lam Stephen, Haigh Jonathan, O'Sullivan Conor, Michaels Kimon, Comensoli Simone, Strojwas Marcin, Rauscher Markus, Kibarian John
Year of Publication 16.01.2018

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Patent

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