Bi-CMOS semiconductor memory device, including improved layout structure and testing method
KOBAYASHI; YUTAKA, NOZOE; ATSUSHI, KINOSHITA; YOSHITAKA, TSUKADA; HIROMI, YANAGISAWA; KAZUMASA, NAKAMURA; MASAYUKI, OUCHI; YOSHIAKI, MIHASHI; KAZUO, ISHII; KYOKO, MATSUMOTO; TETSUROU, WADA; SHOJI, UDAGAWA; TETSU, OHTA; TATSUYUKI, MIWA; HITOSHI, KITSUKAWA; GORO
Year of Publication 22.09.1992
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Year of Publication 22.09.1992
Patent
RESISTANCE MEANS, LOGIC CIRCUIT, INPUT CIRCUIT, FUSE-BLOWING CIRCUIT, DRIVE CIRCUIT, POWER-SUPPLY CIRCUIT AND ELECTROSTATIC PROTECTIVE CIRCUIT; SEMICONDUCTOR STORAGE DEVICE CONTAINING THEM, AND ITS LAYOUT SYSTEM AND TEST SYSTEM
TSUKADA AKIMI, OUCHI YOSHIAKI, KINOSHITA YOSHITAKA, OTA TATSUYUKI, ISHII KYOKO, NAKAMURA MASAYUKI, KOBAYASHI YUTAKA, UDAGAWA SATORU, MIHASHI KAZUO, WADA SHOJI, MIWA HITOSHI, NOZOE ATSUSHI, MATSUMOTO TETSUO, YANAGISAWA KAZUMASA, KITSUKAWA GORO
Year of Publication 01.10.1990
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Year of Publication 01.10.1990
Patent