Design Methodologies for Ternary Logic Circuits
Vudadha, Chetan Kumar, Srinivas, MB
Published in 2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) (01.05.2018)
Published in 2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) (01.05.2018)
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Conference Proceeding
Design of CNFET-based Ternary Conditional Sum Adders using Binary Carry Propagation
Vudadha, Chetan
Published in 2024 IEEE International Symposium on Circuits and Systems (ISCAS) (19.05.2024)
Published in 2024 IEEE International Symposium on Circuits and Systems (ISCAS) (19.05.2024)
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Conference Proceeding
Design of a Ternary Logic Processor Using CNTFET Technology
Gadgil, Sharvani, Sandesh, Goli Naga, Vudadha, Chetan
Published in Circuits, systems, and signal processing (01.09.2024)
Published in Circuits, systems, and signal processing (01.09.2024)
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Journal Article
Synthesis of Ternary Logic Circuits Using 2:1 Multiplexers
Vudadha, Chetan, Surya, Ajay, Agrawal, Saurabh, Srinivas, M. B.
Published in IEEE transactions on circuits and systems. I, Regular papers (01.12.2018)
Published in IEEE transactions on circuits and systems. I, Regular papers (01.12.2018)
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Journal Article
Encoder-Based Optimization of CNFET-Based Ternary Logic Circuits
Vudadha, Chetan, Rajagopalan, Srinivasan, Dusi, Aditya, Phaneendra, P. Sai, Srinivas, M. B.
Published in IEEE transactions on nanotechnology (01.03.2018)
Published in IEEE transactions on nanotechnology (01.03.2018)
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Journal Article
FILA: Fault-Model for Interconnection Links in Application-Specific Network-on-Chip Design
Bhanu, P. Veda, Vudadha, Chetan, Soumya, J.
Published in 2020 IEEE International Symposium on Circuits and Systems (ISCAS) (01.10.2020)
Published in 2020 IEEE International Symposium on Circuits and Systems (ISCAS) (01.10.2020)
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Conference Proceeding
Low Power and High Speed Comparator Design in Quantum-dot Cellular Automata
Khan, Anas, Vudadha, Chetan Kumar
Published in 2023 International Conference on Modeling, Simulation & Intelligent Computing (MoSICom) (07.12.2023)
Published in 2023 International Conference on Modeling, Simulation & Intelligent Computing (MoSICom) (07.12.2023)
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Conference Proceeding
Design of CNFET-based Low-Power Ternary Sequential Logic circuits
Gadgil, Sharvani, Vudadha, Chetan
Published in 2021 IEEE 21st International Conference on Nanotechnology (NANO) (28.07.2021)
Published in 2021 IEEE 21st International Conference on Nanotechnology (NANO) (28.07.2021)
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Conference Proceeding
Energy efficient design of CNFET-based multi-digit ternary adders
Vudadha, Chetan, Parlapalli, Sai Phaneendra, Srinivas, M.B.
Published in Microelectronics (01.05.2018)
Published in Microelectronics (01.05.2018)
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Journal Article
An Optimized Design of Reversible Quantum Comparator
Phaneendra, P. Sai, Vudadha, Chetan, Sreehari, V., Srinivas, M. B.
Published in 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems (01.01.2014)
Published in 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems (01.01.2014)
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Conference Proceeding
Journal Article
An Approximate Full-Adder to Eliminate Carry Propagation in Lower Significant Stage of a Multi-Digit Adder
Sudheshna, Bingumalla, Vudadha, Chetan, Wali, Prashant, Kamath, Gopal Krishna
Published in 2023 International Conference on Computer, Electronics & Electrical Engineering & their Applications (IC2E3) (08.06.2023)
Published in 2023 International Conference on Computer, Electronics & Electrical Engineering & their Applications (IC2E3) (08.06.2023)
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Conference Proceeding
Design of CNTFET-based Ternary Logic circuits using Low power Encoder
T, Siddharth, Gadgil, Sharvani, Vudadha, Chetan
Published in 2022 IEEE International Symposium on Smart Electronic Systems (iSES) (01.12.2022)
Published in 2022 IEEE International Symposium on Smart Electronic Systems (iSES) (01.12.2022)
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Conference Proceeding