An efficient EDAC approach for handling multiple bit upsets in memory array
Goerl, Roger C., Villa, Paulo R.C., Poehls, Letícia B., Bezerra, Eduardo A., Vargas, Fabian L.
Published in Microelectronics and reliability (01.09.2018)
Published in Microelectronics and reliability (01.09.2018)
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Journal Article
Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy
Villa, Paulo R. C., Travessini, Rodrigo, Goerl, Roger C., Vargas, Fabian L., Bezerra, Eduardo A.
Published in Journal of electronic testing (01.02.2019)
Published in Journal of electronic testing (01.02.2019)
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Journal Article
Processor core profiling for SEU effect analysis
Travessini, Rodrigo, Villa, Paulo R. C., Vargas, Fabian L., Bezerra, Eduardo Augusto
Published in 2018 IEEE 19th Latin-American Test Symposium (LATS) (01.03.2018)
Published in 2018 IEEE 19th Latin-American Test Symposium (LATS) (01.03.2018)
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Conference Proceeding
Processor checkpoint recovery for transient faults in critical applications
Villa, Paulo R. C., Travessini, Rodrigo, Vargas, Fabian L., Bezerra, Eduardo A.
Published in 2018 IEEE 19th Latin-American Test Symposium (LATS) (01.03.2018)
Published in 2018 IEEE 19th Latin-American Test Symposium (LATS) (01.03.2018)
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Conference Proceeding
A reconfigurable hardware platform for power converter control systems
Villa, Paulo R. C., Bezerra, Eduardo A., Lettnin, Djones V., Mussa, Samir A.
Published in 2015 IEEE International Conference on Industrial Technology (ICIT) (01.03.2015)
Published in 2015 IEEE International Conference on Industrial Technology (ICIT) (01.03.2015)
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Conference Proceeding
Analysis of single-event upsets in a Microsemi ProAsic3E FPGA
Villa, Paulo R. C., Goerl, Roger C., Vargas, Fabian, Poehls, Leticia B., Medina, Nilberto H., Added, Nemitala, de Aguiar, Vitor A. P., Macchione, Eduardo L. A., Aguirre, Fernando, da Silveira, Marcilei A. G., Bezerra, Eduardo A.
Published in 2017 18th IEEE Latin American Test Symposium (LATS) (01.03.2017)
Published in 2017 18th IEEE Latin American Test Symposium (LATS) (01.03.2017)
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Conference Proceeding
A TMR Strategy with Enhanced Dependability Features Based on a Partial Reconfiguration Flow
Goncalves Martins, Victor M., Villa, Paulo R. C., Neto, Horacio C. C., Bezerra, Eduardo Augusto
Published in 2015 IEEE Computer Society Annual Symposium on VLSI (01.07.2015)
Published in 2015 IEEE Computer Society Annual Symposium on VLSI (01.07.2015)
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Conference Proceeding