Modeling of adders using CMOS and GDI logic for multiplier applications: A VLSI based approach
Rashmi, D. S., Rukhsar, R. Sadiya, Shilpa, H. R., Vidyashree, C. R., Shinde, Kunjan D., Nithin, H. V.
Published in 2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT) (01.03.2016)
Published in 2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT) (01.03.2016)
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Conference Proceeding
A Novel Approach to Design Braun Array Multiplier Using Parallel Prefix Adders for Parallel Processing Architectures: A VLSI Based Approach
Shinde, Kunjan D., Amit Kumar, K., Rashmi, D. S., Sadiya Rukhsar, R., Shilpa, H. R., Vidyashree, C. R.
Published in Soft Computing Systems
Published in Soft Computing Systems
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Book Chapter