Efficient Scheduling of Nested Parallel Loops on Multi-Core Systems
Kejariwal, A., Nicolau, A., Veidenbaum, A.V., Banerjee, U., Polychronopoulos, C.D.
Published in 2009 International Conference on Parallel Processing (01.09.2009)
Published in 2009 International Conference on Parallel Processing (01.09.2009)
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Conference Proceeding
A new pointer-based instruction queue design and its power-performance evaluation
Ramirez, M.A., Cristal, A., Veidenbaum, A.V., Villa, L., Valero, M.
Published in 2005 International Conference on Computer Design (2005)
Published in 2005 International Conference on Computer Design (2005)
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Conference Proceeding
Stride-directed prefetching for secondary caches
Kim, S., Veidenbaum, A.V.
Published in Proceedings of the 1997 International Conference on Parallel Processing (Cat. No.97TB100162) (1997)
Published in Proceedings of the 1997 International Conference on Parallel Processing (Cat. No.97TB100162) (1997)
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Conference Proceeding
Comparative architectural characterization of SPEC CPU2000 and CPU2006 benchmarks on the intel® Core™ 2 Duo processor
Kejariwal, A., Veidenbaum, A.V., Nicolau, A., Tian, X., Girkar, M., Saito, H., Banerjee, U.
Published in 2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (01.07.2008)
Published in 2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (01.07.2008)
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Conference Proceeding
Challenges in exploitation of loop parallelism in embedded applications
Kejariwal, Arun, Veidenbaum, Alexander V., Nicolau, Alexandru, Girkarmark, Milind, Tian, Xinmin, Saito, Hideki
Published in International Conference on Hardware Software Codesign: Proceedings of the 4th international conference on Hardware/software codesign and system synthesis; 22-25 Oct. 2006 (22.10.2006)
Published in International Conference on Hardware Software Codesign: Proceedings of the 4th international conference on Hardware/software codesign and system synthesis; 22-25 Oct. 2006 (22.10.2006)
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Conference Proceeding
Increasing the lookahead of multilevel branch prediction
Veidenbaum, A.V.
Published in Innovative Architecture for Future Generation High-Performance Processors and Systems (1998)
Published in Innovative Architecture for Future Generation High-Performance Processors and Systems (1998)
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Conference Proceeding
Architectural adaptation for power and performance
Weiyu Tang, Veidenbaum, A.V., Gupta, R.
Published in ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549) (2001)
Published in ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549) (2001)
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Conference Proceeding
The effect of limited network bandwidth and its utilization by latency hiding techniques in large-scale shared memory systems
Sunil Kim, Veidenbaum, A.V.
Published in Proceedings 1997 International Conference on Parallel Architectures and Compilation Techniques (1997)
Published in Proceedings 1997 International Conference on Parallel Architectures and Compilation Techniques (1997)
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Conference Proceeding
Direct Instruction Wakeup for Out-of-Order Processors
Ramirez, M.A., Cristal, A., Veidenbaum, A.V., Villa, L., Valero, M.
Published in Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04) (2004)
Published in Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04) (2004)
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Conference Proceeding
Publication
Decoupled access DRAM architecture
Veidenbaum, A.V., Gallivan, K.A.
Published in Proceedings Innovative Architecture for Future Generation High-Performance Processors and Systems (1997)
Published in Proceedings Innovative Architecture for Future Generation High-Performance Processors and Systems (1997)
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Conference Proceeding