Highly Scaled Vertical Cylindrical SONOS Cell With Bilayer Polysilicon Channel for 3-D nand Flash Memory
Van den bosch, G., Kar, G. S., Blomme, P., Arreghini, A., Cacciato, A., Breuil, L., De Keersgieter, A., Paraschiv, V., Vrancken, C., Douhard, B., Richard, O., Van Aerde, S., Debusschere, I., Van Houdt, J.
Published in IEEE electron device letters (01.11.2011)
Published in IEEE electron device letters (01.11.2011)
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Journal Article
Analysis of performance/variability trade-off in Macaroni-type 3-D NAND memory
Congedo, G., Arreghini, A., Liu, L., Capogreco, E., Lisoni, J. G., Huet, K., Toque-Tresonne, I., Van Aerde, S., Toledano-Luque, M., Tan, C.-L, Van den bosch, G., Van Houdt, J.
Published in 2014 IEEE 6th International Memory Workshop (IMW) (01.05.2014)
Published in 2014 IEEE 6th International Memory Workshop (IMW) (01.05.2014)
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Conference Proceeding
Novel Bi-Layer Poly-Silicon Channel Vertical Flash Cell for Ultrahigh Density 3D SONOS NAND Technology
Kar, G S, Van den bosch, G, Cacciato, A, Blomme, P, Arreghini, A, Breuil, L, De Keersgieter, A, Paraschiv, V, Vrancken, C, Douhard, B, Richard, O, Debusschere, I, Van Houdt, J, Van Aerde, S, Baojung Tang
Published in 2011 3rd IEEE International Memory Workshop (IMW) (01.05.2011)
Published in 2011 3rd IEEE International Memory Workshop (IMW) (01.05.2011)
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Conference Proceeding
Novel dual layer floating gate structure as enabler of fully planar flash memory
Blomme, P, Rosmeulen, M, Cacciato, A, Kostermans, M, Vrancken, C, Van Aerde, S, Schram, T, Debusschere, I, Jurczak, M, Van Houdt, J
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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Conference Proceeding
Low Temperature Silcore® Deposition of Undoped and Doped Silicon Films
Fischer, Pamela R., Van Aerde, Steven, Oosterlaken, Ed, Bozon, Bart, Zagwijn, Peter M., Bauer, Matthias, Yan, Min, Verweij, Wilco
Published in ECS transactions (20.10.2006)
Published in ECS transactions (20.10.2006)
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Journal Article
Processing of MEMS gyroscopes on top of CMOS ICs
Witvrouw, A., Mehta, A., Verbist, A., Du Bois, B., Van Aerde, S., Ramos-Martos, J., Ceballos, J., Ragel, A., Mora, J.M., Lagos, M.A., Arias, A., Hinoiosa, J.M., Spengler, J., Leinenbach, C., Fuchs, T., Kronmuller, S.
Published in ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005 (2005)
Published in ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005 (2005)
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Conference Proceeding
A 10 μm thick poly-SiGe gyroscope processed above 0.35 μm CMOS
Scheurle, A., Fuchs, T., Kehr, K., Leinenbach, C., Kronmuller, S., Arias, A., Ceballos, J., Lagos, M.A., Mora, J.M., Munoz, J.M., Ragel, A., Ramos, J., Van Aerde, S., Spengler, J., Mehta, A., Verbist, A., Du Bois, B., Witvrouw, A.
Published in 2007 IEEE 20th International Conference on Micro Electro Mechanical Systems (MEMS) (01.01.2007)
Published in 2007 IEEE 20th International Conference on Micro Electro Mechanical Systems (MEMS) (01.01.2007)
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Conference Proceeding
Method and wafer processing furnace for forming an epitaxial stack of semiconductor epitaxial layers on a plurality of substrates and use of trisilane as semiconductor material precursor
VAN AERDE, STEVEN, JONGBLOED, BERT, DEZELAH, CHARLES, HOUBEN, KELLY, VERWEIJ, WILCO, PIERREUX, DIETER
Year of Publication 16.11.2023
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Year of Publication 16.11.2023
Patent
Semiconductor processing apparatus
PORE, VILJAMI, JONGBLOED, BERT, FUKUDA, HIDEAKI, KNAEPEN, WERNER, VAN AERDE, STEVEN R.A, FUKAZAWA, ATSUKI, PIERREUX, DIETER, HAUKKA, SUVI
Year of Publication 16.06.2024
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Year of Publication 16.06.2024
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Semiconductor device with amorphous silicon filled gaps and methods for forming
JONGBLOED, BERT, HOUBEN, KELLY, VAN AERDE, STEVEN R.A, STOKHOF, MAARTEN, PIERREUX, DIETER
Year of Publication 21.07.2023
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Year of Publication 21.07.2023
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Method of forming epitaxial stacks on multiple substrates
JONGBLOED BERT, VAN AERDE STEVEN, HOUBEN KURT, VERWEIJ WIM, WESTROM PER, PIERROT DAVID
Year of Publication 14.07.2023
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Year of Publication 14.07.2023
Patent
Method of forming epitaxial stack of semiconductor epitaxial layer and wafer processing furnace
JONGBLOED BERT, VAN AERDE STEVEN, HOUBEN KURT, VERWEIJ WIM, PIERROT DAVID, DEZELAH CHARLES
Year of Publication 14.07.2023
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Year of Publication 14.07.2023
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Method for filling a gap
PORE, VILJAMI, JONGBLOED, BERT, FUKUDA, HIDEAKI, KNAEPEN, WERNER, VAN AERDE, STEVEN R.A, FUKAZAWA, ATSUKI, PIERREUX, DIETER, HAUKKA, SUVI
Year of Publication 01.03.2024
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Year of Publication 01.03.2024
Patent
Method and apparatus for filling a gap
PORE, VILJAMI, JONGBLOED, BERT, FUKUDA, HIDEAKI, KNAEPEN, WERNER, VAN AERDE, STEVEN R.A, FUKAZAWA, ATSUKI, PIERREUX, DIETER, HAUKKA, SUVI
Year of Publication 01.11.2023
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Year of Publication 01.11.2023
Patent
Method and apparatus for filling a gap
PORE, VILJAMI, JONGBLOED, BERT, VAN AERDE, STEVEN R. A, FUKUDA, HIDEAKI, KNAEPEN, WERNER, FUKAZAWA, ATSUKI, PIERREUX, DIETER, HAUKKA, SUVI
Year of Publication 01.08.2023
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Year of Publication 01.08.2023
Patent
Method for forming a layer provided with silicon
VAN AERDE, STEVEN R. A, JONGBLOED, BERT, HOUBEN, KELLY, KNAEPEN, WERNER, VERWEIJ, WILCO A, PIERREUX, DIETER
Year of Publication 01.05.2022
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Year of Publication 01.05.2022
Patent
Method and wafer processing furnace for forming an epitaxial stack on a plurality of substrates
VAN AERDE, STEVEN, JONGBLOED, BERT, ELLEUCH, OMAR, WESTROM, PETER, ARYEETEY, FREDERICK, MISKIN, CALEB, HOUBEN, KELLY, KHAZAKA, RAMI, VERWEIJ, WILCO, PIERREUX, DIETER
Year of Publication 01.11.2023
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Year of Publication 01.11.2023
Patent