8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology
KANG, Uksong, CHUNG, Hoe-Ju, LEE, Jae-Wook, JOO, Han-Sung, KIM, Woo-Seop, DONG HYEON JANG, NAM SEOG KIM, CHOI, Jung-Hwan, CHUNG, Tae-Gyeong, YOO, Jei-Hwan, JOO SUN CHOI, KIM, Changhyun, HEO, Seongmoo, JUN, Young-Hyun, PARK, Duk-Ha, LEE, Hoon, JIN HO KIM, AHN, Soon-Hong, CHA, Soo-Ho, AHN, Jaesung, KWON, Dukmin
Published in IEEE journal of solid-state circuits (01.01.2010)
Published in IEEE journal of solid-state circuits (01.01.2010)
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8Gb 3D DDR3 DRAM using through-silicon-via technology
Uksong Kang, Hoe-Ju Chung, Seongmoo Heo, Soon-Hong Ahn, Hoon Lee, Soo-Ho Cha, Jaesung Ahn, DukMin Kwon, Jin Ho Kim, Jae-Wook Lee, Han-Sung Joo, Woo-Seop Kim, Hyun-Kyung Kim, Eun-Mi Lee, So-Ra Kim, Keum-Hee Ma, Dong-Hyun Jang, Nam-Seog Kim, Man-Sik Choi, Sae-Jang Oh, Jung-Bae Lee, Tae-Kyung Jung, Jei-Hwan Yoo, Changhyun Kim
Published in 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers (01.02.2009)
Published in 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers (01.02.2009)
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An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme
Kyu-hyoun Kim, Hoe-Ju Chung, Woo-Seop Kim, Moonsook Park, Jang, Y.-C., Jin-Young Kim, Hwan-Wook Park, Uksong Kang, Coteus, P.W., Joo Sun Choi, Changhyun Kim
Published in IEEE journal of solid-state circuits (01.01.2007)
Published in IEEE journal of solid-state circuits (01.01.2007)
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Session 25 overview: High-bandwidth low-power DRAM and I/O: Memory subcommittee
Kang, Uksong, Sung, James
Published in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (01.02.2014)
Published in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (01.02.2014)
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18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution
Kyomin Sohn, Won-Joo Yun, Reum Oh, Chi-Sung Oh, Seong-Young Seo, Min-Sang Park, Dong-Hak Shin, Won-Chang Jung, Sang-Hoon Shin, Je-Min Ryu, Hye-Seung Yu, Jae-Hun Jung, Kyung-Woo Nam, Seouk-Kyu Choi, Jae-Wook Lee, Uksong Kang, Young-Soo Sohn, Jung-Hwan Choi, Chi-Wook Kim, Seong-Jin Jang, Gyo-Young Jin
Published in 2016 IEEE International Solid-State Circuits Conference (ISSCC) (01.01.2016)
Published in 2016 IEEE International Solid-State Circuits Conference (ISSCC) (01.01.2016)
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A 5.0Gbps/pin packet-based DRAM with low latency receiver and process insensitive PLL
Jung-Hwan Choi, Young-Soo Sohn, Chan-Kyoung Kim, Won-Ki Park, Jae-Hyung Lee, Uksong Kang, Gyung-Su Byun, In-Soo Park, Byung-Chul Kim, Hong-Sun Hwang, Chang-Hyun Kim, Soo-In Cho
Published in Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005 (2005)
Published in Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005 (2005)
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