A thread partitioning algorithm in low power high-level synthesis
Uchida, Jumpei, Togawa, Nozomu, Yanagisawa, Masao, Ohtsuki, Tatsuo
Published in Proceedings of the 2004 Asia and South Pacific Design Automation Conference (27.01.2004)
Published in Proceedings of the 2004 Asia and South Pacific Design Automation Conference (27.01.2004)
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Conference Proceeding
A thread partitioning algorithm in low power high-level synthesis
Uchida, Jumpei, Togawa, Nozomu, Yanagisawa, Masao, Ohtsuki, Tatsuo
Published in with EDA Technofair Design Automation Conference Asia and South Pacific: Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair; 27-30 Jan. 2004 (01.01.2004)
Published in with EDA Technofair Design Automation Conference Asia and South Pacific: Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair; 27-30 Jan. 2004 (01.01.2004)
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Conference Proceeding
An interface-circuit synthesis method with configurable processor core in IP-based SoC designs
Kohara, Shunitsu, Tomono, Naoki, Uchida, Jumpei, Miyaoka, Yuichiro, Togawa, Nozomu, Yanagisawa, Masao, Ohtsuki, Tatsuo
Published in Proceedings of the 2006 Asia and South Pacific Design Automation Conference (24.01.2006)
Published in Proceedings of the 2006 Asia and South Pacific Design Automation Conference (24.01.2006)
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Conference Proceeding
An interface-circuit synthesis method with configurable processor core in IP-based SoC designs
Kohara, S., Tomono, N., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M., Ohtsuki, T.
Published in Asia and South Pacific Conference on Design Automation, 2006 (2006)
Published in Asia and South Pacific Conference on Design Automation, 2006 (2006)
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Conference Proceeding