Mechanisms of interface trap-induced drain leakage current in off-state n-MOSFET's
Chang, Tse-En, Huang, Chimoon, Wang, Tahui
Published in IEEE transactions on electron devices (01.04.1995)
Published in IEEE transactions on electron devices (01.04.1995)
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Journal Article
Interface trap induced thermionic and field emission current in off-state MOSFET's
Wang, Tahui, Chang, Tse-En, Huang, Chimoon
Published in Proceedings of 1994 IEEE International Electron Devices Meeting (1994)
Published in Proceedings of 1994 IEEE International Electron Devices Meeting (1994)
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Conference Proceeding
Journal Article
Mechanisms and characteristics of oxide charge detrapping in n-MOSFET's
Wang, Tahui, Chang, Tse-En, Chiang, Lu-Ping, Huang, Chimoon, Guo, J C
Published in Digest of technical papers - Symposium on VLSI Technology (01.01.1996)
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Published in Digest of technical papers - Symposium on VLSI Technology (01.01.1996)
Journal Article
Investigation of oxide charge trapping and detrapping in a MOSFET by using a GIDL current technique
Wang, T., Chang, T.-E., Chiang, L.-P., Wang, C.-H., Zous, N.-K., Huang, C.
Published in IEEE transactions on electron devices (01.07.1998)
Published in IEEE transactions on electron devices (01.07.1998)
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Journal Article
On the SiO(2)-based gate-dielectric scaling limit forlow-standby power applications in the context of a 0.13 mu m CMOS logictechnology
Lin, Yo-Sheng, Huang, Huan-Tsung, Wu, Chung-Cheng, Leung, Ying-Keung, Pan, Hsu-Yang, Chang, Tse-En, Chen, Wei-Ming, Liaw, Jung-Jih, Diaz, C H
Published in IEEE transactions on electron devices (01.03.2002)
Published in IEEE transactions on electron devices (01.03.2002)
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Journal Article
On the SiO/sub 2/-based gate-dielectric scaling limit for low-standby power applications in the context of a 0.13 μm CMOS logic technology
Yo-Sheng Lin, Huan-Tsung Huang, Chung-Cheng Wu, Ying-Keung Leung, Hsu-Yang Pan, Tse-En Chang, Wei-Ming Chen, Jung-Jih Liaw, Diaz, C.H.
Published in IEEE transactions on electron devices (01.03.2002)
Published in IEEE transactions on electron devices (01.03.2002)
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Journal Article
On the SiO2-based gate-dielectric scaling limit for low-standby power applications in the context of a 0.13 [mu]m CMOS logic technology
Lin, Yo-Sheng, Huang, Huan-Tsung, Wu, Chung-Cheng, Leung, Ying-Keung, Pan, Hsu-Yang, Chang, Tse-En, Chen, Wei-Ming, Liaw, Jung-Jih, Diaz, C.H
Published in IEEE transactions on electron devices (01.03.2002)
Published in IEEE transactions on electron devices (01.03.2002)
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Journal Article
On the SiO/sub 2/-based gate-dielectric scaling limit for low-standby power applications in the context of a 0.13 /spl mu/m CMOS logic technology
Yo-Sheng Lin, Huan-Tsung Huang, Chung-Cheng Wu, Ying-Keung Leung, Hsu-Yang Pan, Tse-En Chang, Wei-Ming Chen, Jung-Jih Liaw, Diaz, C.H.
Published in IEEE transactions on electron devices (01.03.2002)
Published in IEEE transactions on electron devices (01.03.2002)
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Journal Article
On the SiO sub(2)-based gate-dielectric scaling limit for low-standby power applications in the context of a 0.13 mu m CMOS logic technology
Lin, Yo-Sheng, Huang, Huan-Tsung, Wu, Chung-Cheng, Leung, Ying-Keung, Pan, Hsu-Yang, Chang, Tse-En, Chen, Wei-Ming, Liaw, Jung-Jih, Diaz, CH
Published in IEEE transactions on electron devices (01.03.2002)
Published in IEEE transactions on electron devices (01.03.2002)
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Journal Article
Effects of hot carrier induced interface state generation in submicron LDD MOSFET's
Tahui Wang, Chimoon Huang, Chou, P.C., Chung, S.S.-S., Tse-En Chang
Published in IEEE transactions on electron devices (01.09.1994)
Published in IEEE transactions on electron devices (01.09.1994)
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Journal Article
Dopant implantation method using multi-step implants
Chang, Tse-En, Chang, Chih-Fu, Wu, Bone-Fong, Ting, Chieh Chih, Wang, Shao Hua, Chen, Pu-Fang, Chuang, Yen
Year of Publication 30.08.2011
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Year of Publication 30.08.2011
Patent
Dopant implantation method using multi-step implants
WU BONE-FONG, CHUANG YEN, TING CHIEH CHIH, WANG SHAO HUA, CHEN PU-FANG, CHANG TSE-EN, CHANG CHIH-FU
Year of Publication 30.08.2011
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Year of Publication 30.08.2011
Patent
DOPANT IMPLANTATION METHOD AND INTEGRATED CIRCUITS FORMED THEREBY
WU BONE-FONG, CHUANG YEN, TING CHIEH CHIH, WANG SHAO HUA, CHEN PU-FANG, CHANG TSE-EN, CHANG CHIH-FU
Year of Publication 14.01.2010
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Year of Publication 14.01.2010
Patent
Field enhanced oxide charge detrapping in n-MOSFET's
Tahui Wang, Tse-En Chang, Lu-Ping Chiang, Chimoon Huang
Published in Proceedings of International Reliability Physics Symposium (1996)
Published in Proceedings of International Reliability Physics Symposium (1996)
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Conference Proceeding
Mechanisms and characteristics of oxide charge detrapping in n-MOSFETs
Tahui Wang, Tse-En Chang, Lu-Ping Chiang, Chimoon Huang, Guo, J.C.
Published in 1996 Symposium on VLSI Technology. Digest of Technical Papers (1996)
Published in 1996 Symposium on VLSI Technology. Digest of Technical Papers (1996)
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Conference Proceeding