Search Results - "Tsai, Jiunn-Yann" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

Slight gate oxide thickness increase in PMOS devices with BF 2 implanted polysilicon gate

Slight gate oxide thickness increase in PMOS devices with BF 2 implanted polysilicon gate

by Jiunn-Yann Tsai, Ying Shi, Prasad, S., Yeh, S.W.-C., Rakkhit, R.
Published in IEEE electron device letters (01.09.1998)

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Journal Article

A thickness model for the [formula omitted] stack in the titanium salicide process module

A thickness model for the [formula omitted] stack in the titanium salicide process module

by Tsai, Jiunn-Yann, Apte, Pushkar
Published in Thin solid films (01.12.1995)

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Journal Article

A thickness model for the TiSi2/TiN stack in the titanium salicide process module

A thickness model for the TiSi2/TiN stack in the titanium salicide process module

by JIUNN-YANN TSAI, PUSHKAR APTE
Published in Thin solid films (01.12.1995)

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Conference Proceeding

Thickness model for the TiSi sub(2)/TiN stack in the titanium salicide process module

Thickness model for the TiSi sub(2)/TiN stack in the titanium salicide process module

by Tsai, Jiunn-Yann, Apte, Pushkar
Published in Thin solid films (01.01.1995)

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Journal Article

Elevated n(+)/p junctions by implant into CoSi(2)formed on selective epitaxy for deep submicron MOSFETs

Elevated n(+)/p junctions by implant into CoSi(2)formed on selective epitaxy for deep submicron MOSFETs

by Sun, Jie J, Tsai, Jiunn-Yann, Osburn, C M
Published in IEEE transactions on electron devices (01.09.1998)

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Journal Article

Elevated n/sup +//p junctions by implant into CoSi/sub 2/ formed on selective epitaxy for deep submicron MOSFETs

Elevated n/sup +//p junctions by implant into CoSi/sub 2/ formed on selective epitaxy for deep submicron MOSFETs

by Jie J. Sun, Jiunn-Yann Tsai, Osburn, C.M.
Published in IEEE transactions on electron devices (01.09.1998)

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Journal Article

Elevated n super(+)/p junctions by implant into CoSi sub(2) formed on selective epitaxy for deep submicron MOSFET's

Elevated n super(+)/p junctions by implant into CoSi sub(2) formed on selective epitaxy for deep submicron MOSFET's

by Sun, Jie J, Tsai, Jiunn-Yann, Osburn, Carlton M
Published in IEEE transactions on electron devices (01.09.1998)

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Journal Article

Slight gate oxide thickness increase in PMOS devices with BF2 implanted polysilicon gate

Slight gate oxide thickness increase in PMOS devices with BF2 implanted polysilicon gate

by Jiunn-Yann Tsai, Ying Shi, Prasad, S., Yeh, S.W.-C., Rakkhit, R.
Published in IEEE electron device letters (01.09.1998)

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Journal Article

Slight gate oxide thickness increase in PMOS devices with BF(2) implanted polysilicon gate

Slight gate oxide thickness increase in PMOS devices with BF(2) implanted polysilicon gate

by Tsai, Jiunn-Yann, Shi, Ying, Prasad, S, Yeh, S W-C, Rakkhit, R
Published in IEEE electron device letters (01.09.1998)

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Journal Article

Slight gate oxide thickness increase in PMOS devices with BF sub(2) implanted polysilicon gate

Slight gate oxide thickness increase in PMOS devices with BF sub(2) implanted polysilicon gate

by Tsai, Jiunn-Yann, Shi, Ying, Prasad, Sharad, Yeh, Stanley W-C, Rakkhit, Rajat
Published in IEEE electron device letters (01.09.1998)

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Journal Article

DIBL considerations of extended drain structure for 0.1 /spl mu/m MOSFET's

DIBL considerations of extended drain structure for 0.1 /spl mu/m MOSFET's

by Jiunn-Yann Tsai, Jie Sun, Yee, K.F., Osburn, C.M.
Published in IEEE electron device letters (01.07.1996)

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Journal Article

DIBL considerations of extended drain structure for 0.1 mu mMOSFET' s

DIBL considerations of extended drain structure for 0.1 mu mMOSFET' s

by Tsai, Jiunn-Yann, Sun, Jie, Yee, K F, Osburn, C M
Published in IEEE electron device letters (01.07.1996)

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Journal Article

Effect of fluorine incorporation on the thermal stability of PtSi/Si structure

Effect of fluorine incorporation on the thermal stability of PtSi/Si structure

by Tsui, Bing-Yue, Tsai, Jiunn-Yan, Wu, Tzong-Shien, Chen, Mao-Chien
Published in IEEE transactions on electron devices (01.01.1993)

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Journal Article

Local interconnection process for preventing dopant cross diffusion in shared gate electrodes

Local interconnection process for preventing dopant cross diffusion in shared gate electrodes

by Hsia, Shouli, Tsai, Jiunn-Yann
Year of Publication 17.12.2002

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Patent

Local interconnection process for preventing dopant cross diffusion in shared gate electrodes

Local interconnection process for preventing dopant cross diffusion in shared gate electrodes

by HSIA SHOULI, TSAI JIUNN-YANN
Year of Publication 17.12.2002

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Patent

Local interconnection process for preventing dopant cross diffusion in shared gate electrodes

Local interconnection process for preventing dopant cross diffusion in shared gate electrodes

by HSIA; SHOULI, TSAI; JIUNN-YANN
Year of Publication 07.03.2000

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Patent

Process for forming vias, and trenches for metal lines, in multiple dielectric layers of integrated circuit structure

Process for forming vias, and trenches for metal lines, in multiple dielectric layers of integrated circuit structure

by HSIA; SHOULI STEVE, TSAI; JIUNN-YANN
Year of Publication 14.03.2000

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Patent

Process for forming metal silicide contacts using amorphization of exposed silicon while minimizing device degradation

Process for forming metal silicide contacts using amorphization of exposed silicon while minimizing device degradation

by YEH; WENIN, TSAI; JIUNN-YANN, WANG; ZHIHAI
Year of Publication 04.01.2000

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Patent

Optimization of lightly-doped-drain (LDD) structure for sub-quarter-/spl mu/m devices using statistical design and response surface methodology

Optimization of lightly-doped-drain (LDD) structure for sub-quarter-/spl mu/m devices using statistical design and response surface methodology

by Jiunn-Yann Tsai, Zhang, K.X., Osburn, C.M.
Published in 1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (1995)

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Conference Proceeding

Modified multilayered metal line structure for use with tungsten-filled vias in integrated circuit structures

Modified multilayered metal line structure for use with tungsten-filled vias in integrated circuit structures

by HSIA; SHOULI STEVE, CHEN; FRED, TSAI; JIUNN-YANN
Year of Publication 14.11.2000

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Patent