Design Optimization and Modeling of Charge Trap Transistors (CTTs) in 14 nm FinFET Technologies
Khan, Faraz, Han, Min Soo, Moy, Dan, Katz, Robert, Jiang, Liu, Banghart, Edmund, Robson, Norman, Kirihata, Toshiaki, Woo, Jason C. S., Iyer, Subramanian S.
Published in IEEE electron device letters (01.07.2019)
Published in IEEE electron device letters (01.07.2019)
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Journal Article
Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology
Batra, Pooja, Skordas, Spyridon, LaTulipe, Douglas, Winstel, Kevin, Kothandaraman, Chandrasekharan, Himmel, Ben, Maier, Gary, He, Bishan, Gamage, Deepal Wehella, Golz, John
Published in Journal of low power electronics and applications (05.05.2014)
Published in Journal of low power electronics and applications (05.05.2014)
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Journal Article
Prototype of multi-stacked memory wafers using low-temperature oxide bonding and ultra-fine-dimension copper through-silicon via interconnects
Wei Lin, Faltermeier, Johnathan, Winstel, Kevin, Skordas, Spyridon, Graves-Abe, Troy, Batra, Pooja, Herman, Kenneth, Golz, John, Kirihata, Toshiaki, Garant, John, Hubbard, Alex, Cauffman, Kris, Levine, Theodore, Kelly, James, Priyadarshini, Deepika, Peethala, Brown, Patlolla, Raghuveer, Shoudy, Matthew, Demarest, James J., Wynne, Jean, Canaperi, Donald, McHerron, Dale, Berger, Dan, Iyer, Subramanian
Published in 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (01.10.2014)
Published in 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (01.10.2014)
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Conference Proceeding
80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity
Jayaraman, Balaji, Leu, Derek, Viraraghavan, Janakiraman, Cestero, Alberto, Ming Yin, Golz, John, Tummuru, Rajesh Reddy, Raghavan, Ramesh, Moy, Dan, Kempanna, Thejas, Khan, Faraz, Kirihata, Toshiaki, Iyer, Subramanian S.
Published in IEEE journal of solid-state circuits (01.03.2018)
Published in IEEE journal of solid-state circuits (01.03.2018)
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Journal Article
Advanced memory topics
Kirihata, Toshiaki, Somasekhar, Dinesh
Published in Proceedings of the IEEE 2014 Custom Integrated Circuits Conference (01.09.2014)
Published in Proceedings of the IEEE 2014 Custom Integrated Circuits Conference (01.09.2014)
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Conference Proceeding
Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM
Rosenblatt, S., Fainstein, D., Cestero, A., Safran, J., Robson, N., Kirihata, T., Iyer, S. S.
Published in IEEE journal of solid-state circuits (01.04.2013)
Published in IEEE journal of solid-state circuits (01.04.2013)
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Journal Article
Conference Proceeding
A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache
Barth, John, Nair, Kavita, Cao, Nianzheng, Plass, Don, Nelson, Erik, Hwang, Charlie, Fredeman, Gregory, Sperling, Michael, Mathews, Abraham, Kirihata, Toshiaki, Reohr, William R.
Published in IEEE journal of solid-state circuits (01.01.2011)
Published in IEEE journal of solid-state circuits (01.01.2011)
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Journal Article
Conference Proceeding
Advanced memory topics
Niii, Koji, Kirihata, Toshiaki
Published in Proceedings of the IEEE 2013 Custom Integrated Circuits Conference (01.09.2013)
Published in Proceedings of the IEEE 2013 Custom Integrated Circuits Conference (01.09.2013)
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Conference Proceeding
A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access
Fredeman, Gregory, Plass, Donald W., Mathews, Abraham, Viraraghavan, Janakiraman, Reyer, Kenneth, Knips, Thomas J., Miller, Thomas, Gerhard, Elizabeth L., Kannambadi, Dinesh, Paone, Chris, Dongho Lee, Rainey, Daniel J., Sperling, Michael, Whalen, Michael, Burns, Steven, Tummuru, Rajesh Reddy, Ho, Herbert, Cestero, Alberto, Arnold, Norbert, Khan, Babar A., Kirihata, Toshiaki, Iyer, Subramanian S.
Published in IEEE journal of solid-state circuits (01.01.2016)
Published in IEEE journal of solid-state circuits (01.01.2016)
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Journal Article
Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias
Kirihata, Toshiaki, Golz, John, Wordeman, Matthew, Batra, Pooja, Maier, Gary W., Robson, Norman, Graves-abe, Troy L., Berger, Daniel, Iyer, Subramanian S.
Published in IEEE journal on emerging and selected topics in circuits and systems (01.09.2016)
Published in IEEE journal on emerging and selected topics in circuits and systems (01.09.2016)
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Journal Article
14-nm FinFET 1.5 Mb Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Differential Current Sensing
Hunt-Schroeder, Eric, Anand, Darren, Fifield, John, Roberge, Michael, Pontius, Dale, Jacunski, Mark, Batson, Kevin, Deming, Matthew, Khan, Faraz, Moy, Dan, Cestero, Alberto, Katz, Robert, Chbili, Zakariae, Banghart, Edmund, Jiang, Liu, Jayaraman, Balaji, Tummuru, Rajesh R., Raghavan, Ramesh, Mishra, Amit, Robson, Norman, Kirihata, Toshiaki
Published in IEEE solid-state circuits letters (01.12.2018)
Published in IEEE solid-state circuits letters (01.12.2018)
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Journal Article
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
Barth, J., Reohr, W.R., Parries, P., Fredeman, G., Golz, J., Schuster, S.E., Matick, R.E., Hunter, H., Tanner, C.C., Harig, J., Kim Hoki, Khan, B.A., Griesemer, J., Havreluk, R.P., Yanagisawa, K., Kirihata, T., Iyer, S.S.
Published in IEEE journal of solid-state circuits (01.01.2008)
Published in IEEE journal of solid-state circuits (01.01.2008)
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Journal Article
Conference Proceeding
In-situ measurement of variability in 45-nm SOI embedded DRAM arrays
Agarwal, K, Hayes, J, Barth, J, Jacunski, M, Nowka, K, Kirihata, T, Iyer, S
Published in 2010 Symposium on VLSI Circuits (01.06.2010)
Published in 2010 Symposium on VLSI Circuits (01.06.2010)
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Conference Proceeding
A Compact eFUSE Programmable Array Memory for SOI CMOS
Safran, J., Leslie, A., Fredeman, G., Kothandaraman, C., Cestero, A., Xiang Chen, Rajeevakumar, R., Deok-kee Kim, Yan Zun Li, Moy, D., Robson, N., Kirihata, T., Iyer, S.
Published in 2007 IEEE Symposium on VLSI Circuits (01.06.2007)
Published in 2007 IEEE Symposium on VLSI Circuits (01.06.2007)
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Conference Proceeding
Three dimensional dynamic random access memory
Kirihata, Toshiaki
Published in 2014 4th IEEE International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D) (01.07.2014)
Published in 2014 4th IEEE International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D) (01.07.2014)
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Conference Proceeding
Three-dimensional wafer stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology
Batra, Pooja, LaTulipe, Douglas, Skordas, Spyridon, Winstel, Kevin, Kothandaraman, Chandrasekharan, Himmel, Ben, Maier, Gary, He, Bishan, Gamage, Deepal Wehella, Golz, John, Wei Lin, Tuan Vo, Priyadarshini, Deepika, Hubbard, Alex, Cauffman, Kristian, Peethala, Brown, Barth, John, Kirihata, Toshiaki, Graves-Abe, Troy, Robson, Norman, Iyer, Subramanian
Published in 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (01.10.2013)
Published in 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (01.10.2013)
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Conference Proceeding