Search Results - "Toifl, Thomas" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

Wide bandwidth room-temperature THz imaging array based on antenna-coupled MOSFET bolometer

Wide bandwidth room-temperature THz imaging array based on antenna-coupled MOSFET bolometer

by Morf, Thomas, Klein, Bernhard, Despont, Michel, Drechsler, Ute, Kull, Lukas, Corcos, Dan, Elad, Danny, Kaminski, Noam, Pfeiffer, Ullrich R., Al Hadi, Richard, Keller, Hans M., Braendli, Matthias, Menolfi, Christian, Kossel, Marcel, Francese, Pier Andrea, Toifl, Thomas, Plettemeier, Dirk
Published in Sensors and actuators. A. Physical. (15.08.2014)

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Journal Article

A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

by Kull, Lukas, Toifl, Thomas, Schmatz, Martin, Francese, Pier Andrea, Menolfi, Christian, Brandli, Matthias, Kossel, Marcel, Morf, Thomas, Andersen, Toke Meyer, Leblebici, Yusuf
Published in IEEE journal of solid-state circuits (01.12.2013)

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Journal Article Conference Proceeding

A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET

A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET

by Kull, Lukas, Luu, Danny, Menolfi, Christian, Brandli, Matthias, Francese, Pier Andrea, Morf, Thomas, Kossel, Marcel, Cevrero, Alessandro, Ozkaya, Ilter, Toifl, Thomas
Published in IEEE journal of solid-state circuits (01.12.2018)

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Journal Article

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

by Kim, Gain, Kossel, Marcel, Cevrero, Alessandro, Ozkaya, Ilter, Burg, Andreas, Toifl, Thomas, Leblebici, Yusuf, Kull, Lukas, Luu, Danny, Braendli, Matthias, Menolfi, Christian, Francese, Pier-Andrea, Yueksel, Hazar, Aprile, Cosimo, Morf, Thomas
Published in IEEE journal of solid-state circuits (01.01.2020)

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Journal Article

Integrated circuits for particle physics experiments

Integrated circuits for particle physics experiments

by Snoeys, W., Anelli, G., Campbell, M., Cantatore, E., Faccio, F., Heijne, E.H.M., Jarron, P., Kloukinas, K.C., Marchioro, A., Moreira, P., Toifl, T., Wyllie, K.
Published in IEEE journal of solid-state circuits (01.12.2000)

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Journal Article

Session 8 Overview: Ultra-High-Speed Wireline

Session 8 Overview: Ultra-High-Speed Wireline

by Frans, Yohan, Yue, Patrick, Toifl, Thomas
Published in 2021 IEEE International Solid-State Circuits Conference (ISSCC) (13.02.2021)

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Conference Proceeding

Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS

Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS

by Kull, Lukas, Pliva, Jan, Toifl, Thomas, Schmatz, Martin, Francese, Pier Andrea, Menolfi, Christian, Brandli, Matthias, Kossel, Marcel, Morf, Thomas, Andersen, Toke Meyer, Leblebici, Yusuf
Published in IEEE journal of solid-state circuits (01.03.2016)

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Journal Article

A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET

A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET

by Luu, Danny, Kull, Lukas, Toifl, Thomas, Menolfi, Christian, Brandli, Matthias, Francese, Pier Andrea, Morf, Thomas, Kossel, Marcel, Yueksel, Hazar, Cevrero, Alessandro, Ozkaya, Ilter, Huang, Qiuting
Published in IEEE journal of solid-state circuits (01.11.2018)

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Journal Article

An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels

An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels

by Aprile, Cosimo, Cevrero, Alessandro, Francese, Pier Andrea, Menolfi, Christian, Braendli, Matthias, Kossel, Marcel, Morf, Thomas, Kull, Lukas, Oezkaya, Ilter, Leblebici, Yusuf, Cevher, Volkan, Toifl, Thomas
Published in IEEE journal of solid-state circuits (01.03.2018)

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Journal Article

A 10 W On-Chip Switched Capacitor Voltage Regulator With Feedforward Regulation Capability for Granular Microprocessor Power Delivery

A 10 W On-Chip Switched Capacitor Voltage Regulator With Feedforward Regulation Capability for Granular Microprocessor Power Delivery

by Andersen, Toke M., Krismer, Florian, Kolar, Johann W., Toifl, Thomas, Menolfi, Christian, Kull, Lukas, Morf, Thomas, Kossel, Marcel, Brandli, Matthias, Francese, Pier Andrea
Published in IEEE transactions on power electronics (01.01.2017)

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Journal Article

A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET

A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET

by Ozkaya, Ilter, Cevrero, Alessandro, Francese, Pier Andrea, Menolfi, Christian, Morf, Thomas, Brandli, Matthias, Kuchta, Daniel M., Kull, Lukas, Baks, Christian W., Proesel, Jonathan E., Kossel, Marcel, Luu, Danny, Lee, Benjamin G., Doany, Fuad E., Meghelli, Mounir, Leblebici, Yusuf, Toifl, Thomas
Published in IEEE journal of solid-state circuits (01.12.2017)

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Journal Article

Modeling and Pareto Optimization of On-Chip Switched Capacitor Converters

Modeling and Pareto Optimization of On-Chip Switched Capacitor Converters

by Andersen, Toke M., Krismer, Florian, Kolar, Johann W., Toifl, Thomas, Menolfi, Christian, Kull, Lukas, Morf, Thomas, Kossel, Marcel, Brandli, Matthias, Francese, Pier Andrea
Published in IEEE transactions on power electronics (01.01.2017)

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Journal Article

A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS

A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS

by Menolfi, Christian, Toifl, Thomas, Braendli, Matthias, Francese, Pier Andrea, Morf, Thomas, Cevrero, Alessandro, Kossel, Marcel, Kull, Lukas, Luu, Danny, Ozkaya, Ilter
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)

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Conference Proceeding

A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth

A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth

by Francese, Pier Andrea, ToifI, Thomas, Buchmann, Peter, Brändli, Matthias, Menolfi, Christian, Kossel, Marcel, Morf, Thomas, Kull, Lukas, Andersen, Toke Meyer
Published in IEEE journal of solid-state circuits (01.11.2014)

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Journal Article

Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders

Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders

by Yueksel, Hazar, Braendli, Matthias, Burg, Andreas, Cherubini, Giovanni, Cideciyan, Roy D., Francese, Pier Andrea, Furrer, Simeon, Kossel, Marcel, Kull, Lukas, Luu, Danny, Menolfi, Christian, Morf, Thomas, Toifl, Thomas
Published in IEEE transactions on circuits and systems. I, Regular papers (01.10.2018)

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Journal Article

A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET

A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET

by Ozkaya, Ilter, Cevrero, Alessandro, Francese, Pier Andrea, Menolfi, Christian, Morf, Thomas, Brandli, Matthias, Kuchta, Daniel M., Kull, Lukas, Baks, Christian W., Proesel, Jonathan E., Kossel, Marcel, Luu, Danny, Lee, Benjamin G., Doany, Fuad E., Meghelli, Mounir, Leblebici, Yusuf, Toifl, Thomas
Published in IEEE journal of solid-state circuits (01.04.2018)

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Journal Article

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology

by Bulzacchelli, J. F., Menolfi, C., Beukema, T. J., Storaska, D. W., Hertle, J., Hanson, D. R., Ping-Hsuan Hsieh, Rylov, S. V., Furrer, D., Gardellini, D., Prati, A., Morf, T., Sharma, V., Kelkar, R., Ainspan, H. A., Kelly, W. R., Chieco, L. R., Ritter, G. A., Sorice, J. A., Garlett, J. D., Callan, R., Brandli, M., Buchmann, P., Kossel, M., Toifl, T., Friedman, D. J.
Published in IEEE journal of solid-state circuits (01.12.2012)

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Journal Article Conference Proceeding

A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS

A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS

by Reutemann, Robert, Ruegg, Michael, Keyser, Fran, Bergkvist, John, Dreps, Daniel, Toifl, Thomas, Schmatz, Martin
Published in IEEE journal of solid-state circuits (01.12.2010)

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Journal Article Conference Proceeding

F5: Enabling New System Architectures with 2.5D, 3D, and Chiplets

F5: Enabling New System Architectures with 2.5D, 3D, and Chiplets

by Gonzalez, Christopher, Liu, Huichu, Noh, Mijung, Karl, Eric, Toifl, Thomas, Hsu, Shawn
Published in 2021 IEEE International Solid-State Circuits Conference (ISSCC) (13.02.2021)

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Conference Proceeding

A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET

A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET

by Kull, Lukas, Luu, Danny, Menolfi, Christian, Braendli, Matthias, Francese, Pier Andrea, Morf, Thomas, Kossel, Marcel, Cevrero, Alessandro, Ozkaya, Ilter, Toifl, Thomas
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)

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Conference Proceeding

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