New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications
Fujii, Taro, Toi, Takao, Tanaka, Teruhito, Togawa, Katsumi, Kitaoka, Toshiro, Nishino, Kengo, Nakamura, Noritsugu, Nakahara, Hiroki, Motomura, Masato
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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Conference Proceeding
20.3 A 23.9TOPS/W @ 0.8V, 130TOPS AI Accelerator with 16× Performance-Accelerable Pruning in 14nm Heterogeneous Embedded MPU for Real-Time Robot Applications
Nose, Koichi, Fujii, Taro, Togawa, Katsumi, Okumura, Shunsuke, Mikami, Kentaro, Hayashi, Daichi, Tanaka, Teruhito, Toi, Takao
Published in 2024 IEEE International Solid-State Circuits Conference (ISSCC) (18.02.2024)
Published in 2024 IEEE International Solid-State Circuits Conference (ISSCC) (18.02.2024)
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Conference Proceeding
Optimizing time and space multiplexed computation in a dynamically reconfigurable processor
Toi, Takao, Nakamura, Noritsugu, Fujii, Taro, Kitaoka, Toshiro, Togawa, Katsumi, Furuta, Koichiro, Awashima, Toru
Published in 2013 International Conference on Field-Programmable Technology (FPT) (01.12.2013)
Published in 2013 International Conference on Field-Programmable Technology (FPT) (01.12.2013)
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Conference Proceeding