Two-level pipelined systolic arrays for matrix-vector multiplication
MILENTIJEVIC, I. Z, MILOVANOVIC, I. Z, MILOVANOVIC, E. I, TOSIC, M. B, STOJCEV, M. K
Published in Journal of systems architecture (01.02.1998)
Published in Journal of systems architecture (01.02.1998)
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Journal Article
The asynchronous counterflow pipeline bit-serial multiplier
TOSIC, M. B, STOJCEV, M. K, MAKSIMOVIC, D. M, DJORDJEVIC, G. L
Published in Journal of systems architecture (01.09.1998)
Published in Journal of systems architecture (01.09.1998)
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Journal Article