Metrology Challenges for 45-nm Strained-Si Device Technology
Vartanian, V., Zollner, S., Thean, A.V.-Y., White, T., Nguyen, B.-Y., Prabhu, L., Eades, D., Parsons, S., Desjardins, H., Kim, K., Jiang, Z.-X., Dhandapani, V., Hildreth, J., Powers, R., Spencer, G., Ramani, N., Kottke, M., Canonico, M., Wang, X.-D., Contreras, L., Theodore, D., Gregory, R., Venkatesan, S.
Published in IEEE transactions on semiconductor manufacturing (01.11.2006)
Published in IEEE transactions on semiconductor manufacturing (01.11.2006)
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Strain-Enhanced CMOS Through Novel Process-Substrate Stress Hybridization of Super-Critically Thick Strained Silicon Directly on Insulator (SC-SSOI)
Mazure, C., Cayrefourcq, I., Mogab, J., Venkatesan, S., White, B.E., Nguyen, B.-Y., White, T., Burnett, D., La, L.-B., Backer, S., Prabhu, L., Dhandapani, V., Goolsby, B., Wang, X.-D., Goedeke, D., Filipiak, S., Spencer, G., Murphy, S., Shi, Z.-H., Gu, B., Grudowski, P., Desjardin, H., Canonico, M., Conner, J., Adams, V., Vartanian, V., Zhang, D., Thean, A.V.-Y.
Published in 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers (2006)
Published in 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers (2006)
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Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates
Mertens, H., Ritzenthaler, R., Hikavyy, A., Kim, M. S., Tao, Z., Wostyn, K., Chew, S. A., De Keersgieter, A., Mannaert, G., Rosseel, E., Schram, T., Devriendt, K., Tsvetanova, D., Dekkers, H., Demuynck, S., Chasin, A., Van Besien, E., Dangol, A., Godny, S., Douhard, B., Bosman, N., Richard, O., Geypen, J., Bender, H., Barla, K., Mocuta, D., Horiguchi, N., Thean, A. V-Y
Published in 2016 IEEE Symposium on VLSI Technology (01.06.2016)
Published in 2016 IEEE Symposium on VLSI Technology (01.06.2016)
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Ultimate nano-electronics: New materials and device concepts for scaling nano-electronics beyond the Si roadmap
Collaert, N., Alian, A., Arimura, H., Boccardi, G., Eneman, G., Franco, J., Ivanov, Ts, Lin, D., Loo, R., Merckling, C., Mitard, J., Pourghaderi, M.A., Rooyackers, R., Sioncke, S., Sun, J.W., Vandooren, A., Veloso, A., Verhulst, A., Waldron, N., Witters, L., Zhou, D., Barla, K., Thean, A.V.-Y.
Published in Microelectronic engineering (25.01.2015)
Published in Microelectronic engineering (25.01.2015)
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An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates
Waldron, N., Merckling, C., Guo, W., Ong, P., Teugels, L., Ansar, S., Tsvetanova, D., Sebaai, F., van Dorp, D. H., Milenin, A., Lin, D., Nyns, L., Mitard, J., Pourghaderi, A., Douhard, B., Richard, O., Bender, H., Boccardi, G., Caymax, M., Heyns, M., Vandervorst, W., Barla, K., Collaert, N., Thean, A. V.-Y
Published in 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers (01.06.2014)
Published in 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers (01.06.2014)
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Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect
Witters, L., Mitard, J., Loo, R., Demuynck, S., Chew, S. A., Schram, T., Tao, Z., Hikavyy, A., Sun, J. W., Milenin, A. P., Mertens, H., Vrancken, C., Favia, P., Schaekers, M., Bender, H., Horiguchi, N., Langer, R., Barla, K., Mocuta, D., Collaert, N., Thean, A. V.-Y
Published in 2015 Symposium on VLSI Technology (VLSI Technology) (01.06.2015)
Published in 2015 Symposium on VLSI Technology (VLSI Technology) (01.06.2015)
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Strained c:Si0.55Ge0.45 with embedded e:Si0.75Ge0.25 S/D IFQW SiGe-pFET for DRAM periphery applications
Ritzenthaler, R., Schram, T., Witters, L., Mitard, J., Spessot, A., Caillat, C., Hellings, G., Eneman, G., Aoulaiche, M., Na, H.-J., Son, Y., Noh, K.B., Fazan, P., Lee, S.-G., Collaert, N., Mocuta, A., Horiguchi, N., Thean, A.V.-Y.
Published in Materials science in semiconductor processing (01.02.2016)
Published in Materials science in semiconductor processing (01.02.2016)
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Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal
Mertens, H., Ritzenthaler, R., Arimura, H., Franco, J., Sebaai, F., Hikavyy, A., Pawlak, B. J., Machkaoutsan, V., Devriendt, K., Tsvetanova, D., Milenin, A. P., Witters, L., Dangol, A., Vancoille, E., Bender, H., Badaroglu, M., Holsteyns, F., Barla, K., Mocuta, D., Horiguchi, N., Thean, A. V.-Y
Published in 2015 Symposium on VLSI Technology (VLSI Technology) (01.06.2015)
Published in 2015 Symposium on VLSI Technology (VLSI Technology) (01.06.2015)
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Finfet with isolated n+ and p+ gate regions strapped with metal and polysilicon
Mathew, L., Sadd, M., White, B.E., Vandooren, A., Dakshina-Murthy, S., Cobb, J., Stephens, T., Mora, R., Pham, D., Conner, J., White, T., Shi, Z., Thean, A.V.-Y., Barr, A., Zavala, M., Schaeffer, J., Rendon, M.J., Sing, D., Orlowski, M., Nguyen, B.-Y., Mogab, J.
Published in 2003 IEEE International Conference on SOI (2003)
Published in 2003 IEEE International Conference on SOI (2003)
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Conference Proceeding
CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET)
Mathew, L., Du, Y., Thean, A.V.-Y., Sadd, M., Vandooren, A., Parker, C., Stephens, T., Mora, R., Rai, R., Zavala, M., Sing, D., Kalpat, S., Hughes, J., Shimer, R., Jallepalli, S., Workman, G., Zhang, W., Fossum, J.G., White, B.E., Nguyen, B.-Y., Mogab, J.
Published in 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573) (2004)
Published in 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573) (2004)
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Conference Proceeding
Performance and Variability Comparisons between Multi-Gate FETs and Planar SOI Transistors
Thean, A.V.-Y., Shi, Z.-H., Mathew, L., Stephens, T., Desjardin, H., Parker, C., White, T., Stoker, M., Prabhu, L., Garcia, R., Nguyen, B.-Y., Murphy, S., Rai, R., Conner, J., White, B.E., Venkatesan, S.
Published in 2006 International Electron Devices Meeting (2006)
Published in 2006 International Electron Devices Meeting (2006)
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Uniaxial-biaxial stress hybridization for super-critical strained-si directly on insulator (SC-SSOI) PMOS with different channel orientations
Thean, A.V.-Y., Cheek, J., Venkatesan, S., Mogab, J., Chang, C.H., Chiu, Y.H., Tuan, H.C., See, Y.C., Liang, M.S., Sun, Y.C., Prabhu, L., Vartanian, V., Ramon, M., Nguyen, B.-Y., White, T., Collard, H., Xie, Q.-H., Murphy, S.
Published in IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest (2005)
Published in IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest (2005)
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Computer aided design of sub-100 nm strained-Si/Si/sub 1-x/Ge/sub x/ NMOSFET through integrated process and device simulations
Thean, A.V.-Y., Barr, A.L., White, T.R., Shi, Z.-H., Nguyen, B.-Y., Liu, C.-L., Beardmore, K., Jiang, J.Z.-X., Lerma, P., Duda, E., Sadaka, M., Orlowski, M., White, B.E., Mogab, J.
Published in International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003 (2003)
Published in International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003 (2003)
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Conference Proceeding
Fabrication and operation of sub-50 nm strained-Si on Si/sub 1-x/Ge/sub x/ Insulator (SGOI) CMOSFETs
Sadaka, M., Thean, A.V.-Y., Barr, A., Tekleab, D., Kalpat, S., White, T., Nguyen, T., Mora, R., Beckage, P., Jawarani, D., Zollner, S., Kottke, M., Liu, R., Canonico, M., Xie, Q.-H., Wang, X.-D., Parsons, S., Eades, D., Zavala, M., Nguyen, B.-Y., Mazure, C., Mogab, J.
Published in 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573) (2004)
Published in 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573) (2004)
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Conference Proceeding
Performance and reliability of sub-100nm TaSiN metal gate fully-depleted SOI devices with high-k (HfO/sub 2/) gate dielectric
Thean, A.V.-Y., Vandooren, A., Kalpat, S., Du, Y., To, I., Hughes, J., Stephens, T., Goolsby, B., White, T., Barr, A., Mathew, L., Huang, M., Egley, S., Zavala, M., Eades, D., Sphabmixay, K., Schaeffer, J., Triyoso, D., Rossow, M., Roan, D., Pham, D., Rai, R., Murphy, S., Nguyen, B.-Y., White, B.E., Duvallet, A., Dao, T., Mogab, J.
Published in Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004 (2004)
Published in Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004 (2004)
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Conference Proceeding
Multi gated device architectures advances, advantages and challenges
Mathew, L., Yang Du, Thean, A.V.-Y., Sadd, M., Vandooren, A., Parker, C., Stephens, T., Mora, R., Raghav Rai, Zavala, M., Sing, D., Kalpai, S., Hughes, J., Shimer, R., Jallepalli, S., Workman, G., White, B.E., Nguyen, B.-Y., Mogab, A.
Published in 2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) (2004)
Published in 2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) (2004)
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