Design of Testable Reversible Sequential Circuits
Thapliyal, H., Ranganathan, N., Kotiyal, S.
Published in IEEE transactions on very large scale integration (VLSI) systems (01.07.2013)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.07.2013)
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Journal Article
TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test
Chakrabarty, K., Deutsch, S., Thapliyal, H., Fangming Ye
Published in 2012 IEEE International Reliability Physics Symposium (IRPS) (01.04.2012)
Published in 2012 IEEE International Reliability Physics Symposium (IRPS) (01.04.2012)
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Conference Proceeding
A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures
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Book Chapter
Conference Proceeding
Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits
Thapliyal, H., Ranganathan, N.
Published in 2009 22nd International Conference on VLSI Design (01.01.2009)
Published in 2009 22nd International Conference on VLSI Design (01.01.2009)
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Conference Proceeding
Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs
Thapliyal, H., Ranganathan, N.
Published in 2010 23rd International Conference on VLSI Design (01.01.2010)
Published in 2010 23rd International Conference on VLSI Design (01.01.2010)
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Conference Proceeding
Mach-Zehnder interferometer based design of all optical reversible binary adder
Kotiyal, S., Thapliyal, H., Ranganathan, N.
Published in 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE) (01.03.2012)
Published in 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE) (01.03.2012)
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Conference Proceeding
Concurrently testable FPGA design for molecular QCA using conservative reversible logic gate
Thapliyal, H., Ranganathan, N.
Published in 2009 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2009)
Published in 2009 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2009)
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Conference Proceeding
Novel BCD adders and their reversible logic implementation for IEEE 754r format
Thapliyal, H., Kotiyal, S., Srinivas, M.B.
Published in 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06) (2006)
Published in 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06) (2006)
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Conference Proceeding
Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate
Thapliyal, H., Ranganathan, N.
Published in 2009 IEEE Computer Society Annual Symposium on VLSI (01.05.2009)
Published in 2009 IEEE Computer Society Annual Symposium on VLSI (01.05.2009)
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Conference Proceeding
Novel design and reversible logic synthesis of multiplexer based full adder and multipliers
Thapliyal, H., Srinivas, M.B.
Published in 48th Midwest Symposium on Circuits and Systems, 2005 (2005)
Published in 48th Midwest Symposium on Circuits and Systems, 2005 (2005)
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Conference Proceeding
A new design of the reversible subtractor circuit
Thapliyal, H., Ranganathan, N.
Published in 2011 11th IEEE International Conference on Nanotechnology (01.08.2011)
Published in 2011 11th IEEE International Conference on Nanotechnology (01.08.2011)
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Conference Proceeding
Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates
Kotiyal, S., Thapliyal, H., Ranganathan, N.
Published in 2012 IEEE Computer Society Annual Symposium on VLSI (01.08.2012)
Published in 2012 IEEE Computer Society Annual Symposium on VLSI (01.08.2012)
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Conference Proceeding