Novel 2-Bit/Cell Metal–Oxide–Nitride–Oxide–Semiconductor Memory Device with Wrapped-Control-Gate Structure That Achieves Source-Side Hot-Electron Injection
Tomiye, Hideto, Terano, Toshio, Nomoto, Kazumasa, Kobayashi, Toshio
Published in Japanese Journal of Applied Physics (01.07.2005)
Published in Japanese Journal of Applied Physics (01.07.2005)
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Journal Article
A 2.97μm-Pitch Event-Based Vision Sensor with Shared Pixel Front-End Circuitry and Low-Noise Intensity Readout Mode
Niwa, Atsumi, Mochizuki, Futa, Berner, Raphael, Maruyarma, Takuya, Terano, Toshio, Takamiya, Kenichi, Kimura, Yasutaka, Mizoguchi, Kyoji, Miyazaki, Takahiro, Kaizu, Shun, Takahashi, Hirotsugu, Suzuki, Atsushi, Brandli, Christian, Wakabayashi, Hayato, Oike, Yusuke
Published in 2023 IEEE International Solid- State Circuits Conference (ISSCC) (19.02.2023)
Published in 2023 IEEE International Solid- State Circuits Conference (ISSCC) (19.02.2023)
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Conference Proceeding
A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations
Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Imaoka, S., Makino, H., Yamagami, Y., Ishikura, S., Terano, T., Oashi, T., Hashimoto, K., Sebe, A., Okazaki, S., Satomi, K., Akamatsu, H., Shinohara, H.
Published in IEEE journal of solid-state circuits (01.01.2008)
Published in IEEE journal of solid-state circuits (01.01.2008)
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Journal Article
Conference Proceeding
A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues
Ishikura, S., Kurumada, M., Terano, T., Yamagami, Y., Kotani, N., Satomi, K., Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Oashi, T., Makino, H., Shinohara, H., Akamatsu, H.
Published in IEEE journal of solid-state circuits (01.04.2008)
Published in IEEE journal of solid-state circuits (01.04.2008)
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Journal Article
Conference Proceeding
SEMICONDUCTOR MEMORY DEVICE
TAKEMURA, KAZUHIRO, KURUMADA, MAREFUSA, TERANO, TOSHIO, SATOMI, KATSUJI
Year of Publication 04.02.2010
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Year of Publication 04.02.2010
Patent
A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations
Yabuuchi, Makoto, Nii, Koji, Tsukamoto, Yasumasa, Ohbayashi, Shigeki, Imaoka, Susumu, Makino, Hiroshi, Yamagami, Yoshinobu, Ishikura, Satoshi, Terano, Toshio, Oashi, Toshiyuki, Hashimoto, Keiji, Sebe, Akio, Okazaki, Gen, Satomi, Katsuji, Akamatsu, Hironori, Shinohara, Hirofumi
Published in 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (01.02.2007)
Published in 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (01.02.2007)
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Conference Proceeding
Narrow distribution of threshold Voltage in 4-Mbit MONOS memory-cell array with F-N channel write and direct/F-N tunneling erase operation as a single transistor structure
Nakamura, A., Moriya, H., Terano, T., Kosaka, H., Hashiguchi, A., Nomoto, K., Fujiwara, I., Kobayashi, T., Oda, T.
Published in IEEE transactions on electron devices (01.06.2004)
Published in IEEE transactions on electron devices (01.06.2004)
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Journal Article