A robust 45 nm gate-length CMOSFET for 90 nm Hi-speed technology
Lim, K.Y., Chan, V., Rengarajan, R., Lee, H.K., Rovedo, N., Lim, E.H., Yang, S., Jamin, F., Nguyen, P., Lin, W., Lai, C.W., Teh, Y.W., Lee, J., Kim, L., Luo, Z., Ng, H., Sudijono, J., Wann, C., Yang, I.
Published in Solid-state electronics (01.04.2006)
Published in Solid-state electronics (01.04.2006)
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65nm cmos technology for low power applications
Steegen, A., Mo, R., Mann, R., Sun, M.-C., Eller, M., Leake, G., Vietzke, D., Tilke, A., Guarin, F., Fischer, A., Pompl, T., Massey, G., Vayshenker, A., Tan, W.L., Ebert, A., Lin, W., Gao, W., Lian, J., Kim, J.-P., Wrschka, P., Yang, J.-H., Ajmera, A., Knoefler, R., Teh, Y.-W., Jamin, F., Park, J.E., Hooper, K., Griffin, C., Nguyen, P., Klee, V., Ku, V., Baiocco, C., Johnson, G., Tai, L., Benedict, J., Scheer, S., Zhuang, H., Ramanchandran, V., Matusiewicz, G., Lin, Y.-H., Siew, Y.K., Zhang, F., Leong, L.S., Liew, S.L., Park, K.C., Lee, K.-W., Hong, D.H., Choi, S.-M., Kaltalioglu, E., Kim, S.O., Naujok, M., Sherony, M., Cowley, A., Thomas, A., Sudijohno, J., Schiml, T., Ku, J.-H., Yang, I.
Published in IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest (2005)
Published in IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest (2005)
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On the Stick-Breaking Representation for Homogeneous NRMIs
Favaro, S., Lijoi, A., Nava, C., Nipoti, B., Prünster, I., Teh, Y. W.
Published in Bayesian analysis (01.09.2016)
Published in Bayesian analysis (01.09.2016)
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New layout dependency in high-k/Metal Gate MOSFETs
Hamaguchi, M., Nair, D., Jaeger, D., Nishimura, H., Li, W., Na, M., Bernicot, C., Liang, J., Stahrenberg, K., Kim, K., Eller, M., Lee, K., Iwamoto, T., Teh, Y., Mori, S., Takasu, Y., Park, J. H., Song, L., Kim, N., Kohler, S., Kothari, H., Han, J., Miyake, S., Meer, H. V., Arnaud, F., Barla, K., Sherony, M., Donaton, R., Celik, M., Miyashita, K., Narayanan, V., Wachnik, R., Chudzik, M., Sudijono, J., Ku, J., Kim, J. D., Sekine, M., Johnson, S., Neumueller, W., Sampson, R., Kaste, E., Divakaruni, R., Matsuoka, F.
Published in 2011 International Electron Devices Meeting (01.12.2011)
Published in 2011 International Electron Devices Meeting (01.12.2011)
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Interaction of middle-of-line (MOL) temperature and mechanical stress on 90nm hi-speed device performance and reliability
Lim, K.Y., Chan, V., Rengarajan, R., Lee, H.K., Rovedo, N., Lim, E.H., Yang, S., Jamin, F., Nguyen, P., Lin, W., Lai, C.W., Teh, Y.W., Lee, J., Kim, L., Luo, Z., Ng, H., Sudijono, J., Wann, C., Yang, I.
Published in Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005 (2005)
Published in Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005 (2005)
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A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process
Chen, X., Samavedam, S., Narayanan, V., Stein, K., Hobbs, C., Baiocco, C., Li, W., Jaeger, D., Zaleski, M., Yang, H. S., Kim, N., Lee, Y., Zhang, D., Kang, L., Chen, J., Zhuang, H., Sheikh, A., Wallner, J., Aquilino, M., Han, J., Jin, Z., Li, J., Massey, G., Kalpat, S., Jha, R., Moumen, N., Mo, R., Kirshnan, S., Wang, X., Chudzik, M., Chowdhury, M., Nair, D., Reddy, C., Teh, Y. W., Kothandaraman, C., Coolbaugh, D., Pandey, S., Tekleab, D., Thean, A., Sherony, M., Lage, C., Sudijono, J., Lindsay, R., Ku, J. H., Khare, M., Steegen, A.
Published in 2008 Symposium on VLSI Technology (01.06.2008)
Published in 2008 Symposium on VLSI Technology (01.06.2008)
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Energy-Based Models for Sparse Overcomplete Representations
Teh, Yee Whye, Welling, Max, Hinton, Geoffrey E
Published in Journal of machine learning research (01.10.2004)
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Published in Journal of machine learning research (01.10.2004)
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Stress Proximity Technique for Performance Improvement with Dual Stress Liner at 45nm Technology and Beyond
Davis, C., Ku, J.H., Schiml, T., Sudijono, J., Yang, I., Steegen, A., Coolbough, D., Hierlemann, M., Ng, H., Amos, R., Sherony, M., Belyansky, M., Widodo, J., Tjoa, T., Edleman, N., Kwon, O., Panda, S., Yuan, J., Nguyen, P., Nivo, N., Luo, Z., Chidambarrao, D., Stierstorfer, R., Kim, J., Park, J., Ajmera, A., Baiocco, C., Ko, Y., Tan, S.S., Teh, Y.W., Dyer, T., Gao, W., Fang, S., Chen, X., Davis, C., Ku, J.H., Schiml, T., Sudijono, J., Yang, I., Steegen, A., Coolbough, D., Hierlemann, M., Ng, H., Amos, R., Sherony, M., Belyansky, M., Widodo, J., Tjoa, T., Edleman, N., Kwon, O., Panda, S., Yuan, J., Nguyen, P., Nivo, N., Luo, Z., Chidambarrao, D., Stierstorfer, R., Kim, J., Park, J., Ajmera, A., Baiocco, C., Ko, Y., Tan, S.S., Teh, Y.W., Dyer, T., Gao, W., Fang, S., Chen, X.
Published in 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers (2006)
Published in 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers (2006)
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Data mining techniques in materialised project and selection view
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Strain for CMOS performance improvement
Chan, V., Ken Rim, Meikei Ieong, Sam Yang, Rajeev Malik, Young Way Teh, Min Yang, Qiqing
Published in Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005 (2005)
Published in Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005 (2005)
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Conference Proceeding
Scaling of 32nm low power SRAM with high-K metal gate
Yang, H.S., Wong, R., Hasumi, R., Gao, Y., Kim, N.S., Lee, D.H., Badrudduza, S., Nair, D., Ostermayr, M., Kang, H., Zhuang, H., Li, J., Kang, L., Chen, X., Thean, A., Arnaud, F., Zhuang, L., Schiller, C., Sun, D.P., Teh, Y.W., Wallner, J., Takasu, Y., Stein, K., Samavedam, S., Jaeger, D., Baiocco, C.V., Sherony, M., Khare, M., Lage, C., Pape, J., Sudijono, J., Steegen, A.L., Stiffler, S.
Published in 2008 IEEE International Electron Devices Meeting (01.12.2008)
Published in 2008 IEEE International Electron Devices Meeting (01.12.2008)
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