Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory
Kim, Sung, Fayazi, Morteza, Daftardar, Alhad, Chen, Kuan-Yu, Tan, Jielun, Pal, Subhankar, Ajayi, Tutu, Xiong, Yan, Mudge, Trevor, Chakrabarti, Chaitali, Blaauw, David, Dreslinski, Ronald, Kim, Hun-Seok
Published in IEEE journal of solid-state circuits (01.04.2022)
Published in IEEE journal of solid-state circuits (01.04.2022)
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Journal Article
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator
Park, Dong-Hyeon, Pal, Subhankar, Feng, Siying, Gao, Paul, Tan, Jielun, Rovinski, Austin, Xie, Shaolin, Zhao, Chun, Amarnath, Aporva, Wesley, Timothy, Beaumont, Jonathan, Chen, Kuan-Yu, Chakrabarti, Chaitali, Taylor, Michael Bedford, Mudge, Trevor, Blaauw, David, Kim, Hun-Seok, Dreslinski, Ronald G.
Published in IEEE journal of solid-state circuits (01.04.2020)
Published in IEEE journal of solid-state circuits (01.04.2020)
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Journal Article
R2D3: A Reliability Engine for 3D Parallel Systems
Bagherzadeh, Javad, Amarnath, Aporva, Tan, Jielun, Pal, Subhankar, Dreslinski, Ronald G.
Published in 2020 57th ACM/IEEE Design Automation Conference (DAC) (01.07.2020)
Published in 2020 57th ACM/IEEE Design Automation Conference (DAC) (01.07.2020)
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Conference Proceeding
3DTUBE: A Design Framework for High-Variation Carbon Nanotube-based Transistor Technology
Amarnath, Aporva, Bagherzadeh, Javad, Tan, Jielun, Dreslinski, Ronald G.
Published in 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) (01.07.2019)
Published in 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) (01.07.2019)
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Conference Proceeding
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm
Pal, Subhankar, Park, Dong-hyeon, Feng, Siying, Gao, Paul, Tan, Jielun, Rovinski, Austin, Xie, Shaolin, Zhao, Chun, Amarnath, Aporva, Wesley, Timothy, Beaumont, Jonathan, Chen, Kuan-Yu, Chakrabarti, Chaitali, Taylor, Michael, Mudge, Trevor, Blaauw, David, Kim, Hun-Seok, Dreslinski, Ronald
Published in 2019 Symposium on VLSI Circuits (01.06.2019)
Published in 2019 Symposium on VLSI Circuits (01.06.2019)
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Conference Proceeding
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm
Pal, Subhankar, Park, Dong-hyeon, Feng, Siying, Gao, Paul, Tan, Jielun, Rovinski, Austin, Xie, Shaolin, Zhao, Chun, Amarnath, Aporva, Wesley, Timothy, Beaumont, Jonathan, Chen, Kuan-Yu, Chakrabarti, Chaitali, Taylor, Michael, Mudge, Trevor, Blaauw, David, Kim, Hun-Seok, Dreslinski, Ronald
Published in 2019 Symposium on VLSI Technology (01.06.2019)
Published in 2019 Symposium on VLSI Technology (01.06.2019)
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Conference Proceeding
Teaching Out-of-Order Processor Design with the RISC-V ISA
Zekany, Stephen A., Tan, Jielun, Connolly, James A.
Published in 2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE) (17.06.2021)
Published in 2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE) (17.06.2021)
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Conference Proceeding
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm
Kim, Sung, Fayazi, Morteza, Daftardar, Alhad, Chen, Kuan-Yu, Tan, Jielun, Pal, Subhankar, Ajayi, Tutu, Xiong, Yan, Mudge, Trevor, Chakrabarti, Chaitali, Blaauw, David, Dreslinski, Ronald, Kim, Hun-Seok
Published in 2021 Symposium on VLSI Circuits (13.06.2021)
Published in 2021 Symposium on VLSI Circuits (13.06.2021)
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Conference Proceeding
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm
Kim, Sung, Fayazi, Morteza, Daftardar, Alhad, Kuan-Yu, Chen, Tan, Jielun, Pal, Subhankar, Ajayi, Tutu, Xiong, Yan, Mudge, Trevor, Chakrabarti, Chaitali, Blaauw, David, Dreslinski, Ronald, Hun-Seok Kim
Published in arXiv.org (01.08.2021)
Published in arXiv.org (01.08.2021)
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Paper
Journal Article