Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation
Zergainoh, N.-E., Tambour, L., Jerraya, A.A.
Published in IEEE transactions on very large scale integration (VLSI) systems (01.04.2006)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.04.2006)
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Journal Article
Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems
Zergainoh, Nacer-Eddine, Tambour, Ludovic, Urard, Pascal, Jerraya, Ahmed Amine
Published in EURASIP Journal on Advances in Signal Processing (01.01.2006)
Published in EURASIP Journal on Advances in Signal Processing (01.01.2006)
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Journal Article
An efficient methodology and semi-automated flow for design and validation of complex digital signal processing ASICS macro-cells
Tambour, L., Zergainoh, N., Urard, P., Michel, H., Jerraya, A.A.
Published in 14th IEEE International Workshop on Rapid Systems Prototyping, 2003. Proceedings (2003)
Published in 14th IEEE International Workshop on Rapid Systems Prototyping, 2003. Proceedings (2003)
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Conference Proceeding