Search Results - "TSOU LEN Y" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

SEMICONDUCTOR INTER-FIELD DOSE CORRECTION

SEMICONDUCTOR INTER-FIELD DOSE CORRECTION

by TSOU LEN Y, ZHUANG HAOREN, YU, DONG HEE, LEE, HYUNG RAE
Year of Publication 22.04.2011

Get full text

Patent

Semiconductor inter-field dose correction

Semiconductor inter-field dose correction

by Lee, Hyung-Rae, Yu, Dong hee, Tsou, Len Y, Zhuang, Haoren
Year of Publication 10.07.2012

Get full text

Patent

Semiconductor inter-field dose correction

Semiconductor inter-field dose correction

by TSOU LEN Y, ZHUANG HAOREN, YU DONG HEE, LEE HYUNG-RAE
Year of Publication 10.07.2012

Get full text

Patent

SEMICONDUCTOR INTER-FIELD DOSE CORRECTION

SEMICONDUCTOR INTER-FIELD DOSE CORRECTION

by TSOU LEN Y, ZHUANG HAOREN, YU DONG HEE, LEE HYUNG-RAE
Year of Publication 21.04.2011

Get full text

Patent

Reactive ion etching or indium tin oxide

Reactive ion etching or indium tin oxide

by TSOU; LEN Y
Year of Publication 15.02.1994

Get full text

Patent

Method for uniform reactive ion etching of dual pre-doped polysilicon regions

Method for uniform reactive ion etching of dual pre-doped polysilicon regions

by Liu, Joyce C, Tsou, Len Y, Yang, Qingyun
Year of Publication 07.12.2004

Get full text

Patent

Method for uniform reactive ion etching of dual pre-doped polysilicon regions

Method for uniform reactive ion etching of dual pre-doped polysilicon regions

by TSOU LEN Y, LIU JOYCE C, YANG QINGYUN
Year of Publication 07.12.2004

Get full text

Patent

PROCESS AND SYSTEM FOR ETCHING DOPED SILICON

PROCESS AND SYSTEM FOR ETCHING DOPED SILICON

by KO, AKITERU, KAPLITA, GEORGE, A, YAN, HONGWEN, TSOU, LEN, Y, RANADE, RAJIV, M, WISE, RICH
Year of Publication 07.05.2009

Get full text

Patent

Method to form gate conductor structures of dual doped polysilicon

Method to form gate conductor structures of dual doped polysilicon

by Brown, Jeffrey J, Tsou, Len Y, Yang, Qingyun
Year of Publication 09.03.2004

Get full text

Patent

Method to form gate conductor structures of dual doped polysilicon

Method to form gate conductor structures of dual doped polysilicon

by TSOU LEN Y, BROWN JEFFREY J, YANG QINGYUN
Year of Publication 09.03.2004

Get full text

Patent

Method to form gate conductor structures of dual doped polysilicon

Method to form gate conductor structures of dual doped polysilicon

by TSOU LEN Y, BROWN JEFFREY J, YANG QINGYUN
Year of Publication 02.10.2003

Get full text

Patent

Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch

Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch

by Tsou, Len Y, Yan, Hongwen, Yang, Qingyun, Yu, Chienfan
Year of Publication 21.01.2003

Get full text

Patent

PROCESS AND SYSTEM FOR ETCHING DOPED SILICON

PROCESS AND SYSTEM FOR ETCHING DOPED SILICON

by KO, AKITERU, KAPLITA, GEORGE, A, YAN, HONGWEN, TSOU, LEN, Y, RANADE, RAJIV, M, WISE, RICH
Year of Publication 12.04.2007

Get full text

Patent

Process and system for etching doped silicon

Process and system for etching doped silicon

by TSOU LEN Y, KAPLITA GEORGE A, RANADE RAJIV M, KO AKITERU, WISE RICH, YAN HONGWEN
Year of Publication 15.03.2007

Get full text

Patent

Method of making sub-lithographic features

Method of making sub-lithographic features

by Deshpande, Sadanand V, Furukawa, Toshiharu, Horak, David V, Natzle, Wesley C, Sekiguchi, Akihisa, Tsou, Len Y, Yang, Qingyun
Year of Publication 01.11.2005

Get full text

Patent

Method of making sub-lithographic features

Method of making sub-lithographic features

by NATZLE WESLEY C, TSOU LEN Y, HORAK DAVID V, FURUKAWA TOSHIHARU, SEKIGUCHI AKIHISA, YANG QINGYUN, DESHPANDE SADANAND V
Year of Publication 01.11.2005

Get full text

Patent

Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching

Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching

by Brown, Jeffrey J, Deshpande, Sadanand Vinayak, Horak, David V, Surendra, Maheswaran, Tsou, Len Y, Yang, Qingyun, Yu, Chienfan, Zhang, Ying
Year of Publication 08.03.2005

Get full text

Patent

Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch

Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch

by TSOU LEN Y, YU CHIENFAN, YAN HONGWEN, YANG QINGYUN
Year of Publication 21.01.2003

Get full text

Patent

Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch

Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch

by TSOU LEN Y, YU CHIENFAN, YAN HONGWEN, YANG QINGYUN
Year of Publication 19.09.2002

Get full text

Patent

Method of making sub-lithographic features

Method of making sub-lithographic features

by NATZLE WESLEY C, TSOU LEN Y, HORAK DAVID V, FURUKAWA TOSHIHARU, SEKIGUCHI AKIHISA, YANG QINGYUN, DESHPANDE SADANAND V
Year of Publication 01.01.2004

Get full text

Patent