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"TSAI, JIA-SHIUNG"
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"TSAI, JIA-SHIUNG"
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Method of top rounding in shallow trench etch
by
CHEN, JAUNG
,
TSAI
,
JIA
-
SHIUNG
Year of Publication
01.01.2001
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Method for improving the metal wire width in integrated circuit
by
SHUE, SHAU-LIN
,
TSAI
,
JIA
-
SHIUNG
Year of Publication
11.03.2001
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Method for forming gate electrode
by
TAO, HUN-JAN
,
TSAI
,
JIA
-
SHIUNG
Year of Publication
21.12.2000
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Dry etching method of the silicon dioxide
by
TAU, HUNG-YUAN
,
TSAI
,
JIA
-
SHIUNG
Year of Publication
11.09.2000
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Taped silicon dioxide etching method with high selectivity on silicon nitride
by
TSAI
,
JIA
-
SHIUNG
,
TAU, HUNG-YUAN
Year of Publication
21.07.2000
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Method of cleaning after etching of gate in integrated circuit
by
HUANG, YUANANG
,
TAU, HUNG-YUAN
,
TSAI
,
JIA
-
SHIUNG
Year of Publication
11.02.2001
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The spacer process for isolating self-alignment contact (SAC) opening
by
LIOU, RENNG
,
LIU, JEN-SHIANG
,
TSAI
,
JIA
-
SHIUNG
Year of Publication
21.09.2000
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Post etching treatment process for dry etcher
by
YANG, BAU-RU
,
TSAI
,
JIA
-
SHIUNG
Year of Publication
11.08.2000
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Method for producing interconnection by contact and trench etching
by
CHEN, JAUNG
,
TAU, HUNG-YUAN
,
TSAI
,
JIA
-
SHIUNG
Year of Publication
01.05.2000
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Selective etching method
by
YU, JEN-HUA
,
TSAI
,
JIA
-
SHIUNG
Year of Publication
01.04.2000
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DRAM manufacturing method
by
BAI, JR-YANG
,
YOU, JR-SHING
,
TSAI
,
JIA
-
SHIUNG
Year of Publication
01.03.2003
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Hard mask etching process without polymer residue
by
HUANG, MING-SHIN
,
YANG, BAU-RU
,
TSAI
,
JIA
-
SHIUNG
Year of Publication
21.11.2002
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Dry development method for bi-layer resist manufacture process
by
WANG, YING-YING
,
YANG, BAU-RU
,
TSAI
,
JIA
-
SHIUNG
Year of Publication
01.09.2002
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Manufacturing method of dual damascene structure
by
LIOU, RENNG
,
LIU, MING-HUEI
,
TAU, HUNG-YUAN
,
TSAI
,
JIA
-
SHIUNG
Year of Publication
21.07.2002
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Spiral inductor containing erect capacitor structures inside
by
JI, MING-HUA
,
DU, YOU-LUEN
,
TSAI
,
JIA
-
SHIUNG
Year of Publication
01.07.2002
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Method for forming isolation gap between bit line and capacitor
by
JI, MING-HUA
,
DU, YOU-LUEN
,
TSAI
,
JIA
-
SHIUNG
Year of Publication
11.06.2002
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Method for manufacturing alternate fin capacitor in dynamic random access memory
by
BAI, JR-YANG
,
YOU, JR-SHING
,
TSAI
,
JIA
-
SHIUNG
Year of Publication
11.03.2002
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Method to manufacture MIM capacitor by dual damascene process
by
JI, MING-HUA
,
DU, YOU-LUEN
,
TSAI
,
JIA
-
SHIUNG
Year of Publication
11.10.2001
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Manufacturing method of dual damascene
by
SHIE, HUNG-JANG
,
LIOU, RENNG
,
GUO, JENG-JENG
,
TSAI
,
JIA
-
SHIUNG
Year of Publication
16.06.2001
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Method for forming contact holes by etching material with low dielectric constant
by
HUANG, MING-SHIN
,
CHEN, JAUNG
,
TAU, HUNG-YUAN
,
TSAI
,
JIA
-
SHIUNG
Year of Publication
01.05.2001
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