Programmable clock data recovery (CDR) system including multiple phase error control paths
Li, Shenggao, De Vita, Michael, Spagna, Fulvio, Chen, Ji, Tong, Guluke
Year of Publication 31.12.2019
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Year of Publication 31.12.2019
Patent
A low power high linearity phase interpolator design for high speed IO interfaces
Katare, Siddharth, Iyer, Sitaraman V., Tong, Guluke, Munagala, Lasya R., Nagarajan, Mahalingam, Bangda, Yang
Published in 2014 International SoC Design Conference (ISOCC) (01.11.2014)
Published in 2014 International SoC Design Conference (ISOCC) (01.11.2014)
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Conference Proceeding
PROGRAMMBLE CLOCK DATA RECOVERY (CDR) SYSTEM INCLUDING MULTIPLE PHASE ERROR CONTROL PATHS
Li, Shenggao, De Vita, Michael, Spagna, Fulvio, Chen, Ji, Tong, Guluke
Year of Publication 03.10.2019
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Year of Publication 03.10.2019
Patent
PROGRAMMABLE CLOCK DATA RECOVERY (CDR) SYSTEM
TONG, Guluke, SPAGNA, Fulvio, LI, Shenggao, CHEN, Ji, DE VITA, Michael
Year of Publication 03.10.2019
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Year of Publication 03.10.2019
Patent
PROGRAMMIERBARES TAKTDATENWIEDERHERSTELLUNGS- (CDR) SYSTEM
Li, Shenggao, De Vita, Michael, Spagna, Fulvio, Chen, Ji, Tong, Guluke
Year of Publication 15.10.2020
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Year of Publication 15.10.2020
Patent