Scaling down and reliability problems of gigabit CMOS circuits
Get full text
Book Review
Journal Article
Influence of the series resistance of on-chip power supply buses on internal device failure after ESD stress (MOS devices)
Terletzki, H., Nikutta, W., Reczek, W.
Published in I.E.E.E. transactions on electron devices (01.11.1993)
Published in I.E.E.E. transactions on electron devices (01.11.1993)
Get full text
Journal Article
Conference Proceeding
A 390-mm/sup 2/, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture
Kirihata, T., Mueller, G., Ji, B., Frankowsky, G., Ross, J.M., Terletzki, H., Netis, D.G., Weinfurtner, O., Hanson, D.R., Daniel, G., Hsu, L.L.-C., Sotraska, D.W., Reith, A.M., Hug, M.A., Guay, K.P., Selz, M., Poechmueller, P., Hoenigschmid, H., Wordeman, M.R.
Published in IEEE journal of solid-state circuits (01.11.1999)
Published in IEEE journal of solid-state circuits (01.11.1999)
Get full text
Journal Article
A 113mm super(2) 600Mb/s/pin 512Mb DDR2 SDRAM with vertically-folded bitline architecture
Kirihata, T, Mueller, G, Clinton, M, Loeffler, S, Ji, B, Terletzki, H, Hanson, D, Hwang, C-L, Lehmann, G, Storaska, D, Daniel, G, Hsu, L, Weinfurtner, O, Boehler, T, Schnell, J
Published in Digest of technical papers - IEEE International Solid-State Circuits Conference (01.01.2001)
Get full text
Published in Digest of technical papers - IEEE International Solid-State Circuits Conference (01.01.2001)
Journal Article
A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs
Hoenigschmid, H, Frey, A, DeBrosse, J.K, Kirihata, T, Mueller, G, Storaska, D.W, Daniel, G, Frankowsky, G, Guay, K.P, Hanson, D.R, Hsu, L.L.-C, Ji, B, Netis, D.G, Panaroni, S, Radens, C, Reith, A.M, Terletzki, H, Weinfurtner, O, Alsmeier, J, Weber, W, Wordeman, M.R
Published in IEEE journal of solid-state circuits (01.05.2000)
Published in IEEE journal of solid-state circuits (01.05.2000)
Get full text
Journal Article
A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs
Hoenigschmid, H., Frey, A., DeBrosse, J.K., Kirihata, T., Mueller, G., Storaska, D.W., Daniel, G., Frankowsky, G., Guay, K.P., Hanson, D.R., Hsu, L.L.-C., Ji, B., Netis, D.G., Panaroni, S., Radens, C., Reith, A.M., Terletzki, H., Weinfurtner, O., Alsmeier, J., Weber, W., Wordeman, M.R.
Published in IEEE journal of solid-state circuits (01.05.2000)
Published in IEEE journal of solid-state circuits (01.05.2000)
Get full text
Journal Article
A 7F(2) cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs
Hoenigschmid, H, Frey, A, DeBrosse, J K, Kirihata, T, Mueller, G, Storaska, D W, Daniel, G, Frankowsky, G, Guay, K P, Hanson, D R, Hsu, L L-C, Ji, B, Netis, D G, Panaroni, S, Radens, C, Reith, A M, Terletzki, H, Weinfurtner, O, Alsmeier, J
Published in IEEE journal of solid-state circuits (01.05.2000)
Published in IEEE journal of solid-state circuits (01.05.2000)
Get full text
Journal Article
A 7F super(2) cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs
Hoenigschmid, H, Frey, A, DeBrosse, J K, Kirihata, T, Mueller, G, Storaska, D W, Daniel, G, Frankowsky, G, Guay, K P, Hanson, DR, Hsu, LL-C, Ji, B, Netis, D G, Panaroni, S, Radens, C, Reith, A M, Terletzki, H, Weinfurtner, O, Alsmeier, J, Weber, W, Wordeman, M R
Published in IEEE journal of solid-state circuits (01.01.2000)
Published in IEEE journal of solid-state circuits (01.01.2000)
Get full text
Journal Article
A 220-mm/sup 2/, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture
Kirihata, T., Gall, M., Hosokawa, K., Dortu, J.-M., Hing Wong, Pfefferi, P., Ji, B.L., Weinfurtner, O., DeBrosse, J.K., Terletzki, H., Selz, M., Ellis, W., Wordeman, M.R., Kiehl, O.
Published in IEEE journal of solid-state circuits (01.11.1998)
Published in IEEE journal of solid-state circuits (01.11.1998)
Get full text
Journal Article
A 220-mm(2), four-and eight-bank, 256-Mb SDRAM withsingle-sided stitched WL architecture
Kirihata, T, Gall, M, Hosokawa, K, Dortu, J-M, Wong, Hing, Pfefferi, P, Ji, B L, Weinfurtner, O, DeBrosse, J K, Terletzki, H, Selz, M, Ellis, W, Wordeman, M R, Kiehl, O
Published in IEEE journal of solid-state circuits (01.11.1998)
Published in IEEE journal of solid-state circuits (01.11.1998)
Get full text
Journal Article
A 390-mm(2), 16-bank, 1-Gb DDR SDRAM with hybrid bitlinearchitecture
Kirihata, T, Mueller, G, Ji, B, Frankowsky, G, Ross, J M, Terletzki, H, Netis, D G, Weinfurtner, O, Hanson, D R, Daniel, G, Hsu, L L-C, Sotraska, D W, Reith, A M, Hug, M A, Guay, K P, Selz, M, Poechmueller, P, Hoenigschmid, H, Wordeman, M R
Published in IEEE journal of solid-state circuits (01.11.1999)
Published in IEEE journal of solid-state circuits (01.11.1999)
Get full text
Journal Article
A 390-mm super(2), 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture
Kirihata, T, Mueller, G, Ji, B, Frankowsky, G, Ross, J M, Terletzki, H, Netis, D G, Weinfurtner, O, Hanson, DR, Daniel, G, Hsu, LL-C, Sotraska, D W, Reith, A M, Hug, MA, Guay, K P, Selz, M, Poechmueller, P, Hoenigschmid, H, Wordeman, M R
Published in IEEE journal of solid-state circuits (01.01.1999)
Published in IEEE journal of solid-state circuits (01.01.1999)
Get full text
Journal Article
220 mm super(2) 4 and 8 bank 256 Mb SDRAM with single-sided stitched WL architecture
Kirihata, T, Gall, M, Hosokawa, K, Dortu, J-M, Wong, H, Pfefferl, K-P, Ji, B, Weinfurtner, O, DeBrosse, J, Terletzki, H, Selz, M, Ellis, W, Wordeman, M, Kiehl, O
Published in Digest of technical papers - IEEE International Solid-State Circuits Conference (01.01.1998)
Get full text
Published in Digest of technical papers - IEEE International Solid-State Circuits Conference (01.01.1998)
Journal Article
Reliability problems of submicron MOS transistors and circuits
Krautschneider, Wolfgang H., Terletzki, Hartmud, Wang, Qin
Published in Microelectronics and reliability (01.11.1992)
Published in Microelectronics and reliability (01.11.1992)
Get full text
Journal Article
Electrostatic discharge test structures for CMOS circuits
Terletzki, H., Risch, L.
Published in Proceedings of the 1989 International Conference on Microelectronic Test Structures (1989)
Published in Proceedings of the 1989 International Conference on Microelectronic Test Structures (1989)
Get full text
Conference Proceeding
A 113 mm/sup 2/ 600 Mb/s/pin 512 Mb DDR2 SDRAM with vertically-folded bitline architecture
Kirihata, T., Mueller, G., Clinton, M., Loeffler, S., Ji, B., Terletzki, H., Hanson, D., Chorng-Lil Hwang, Lehmann, G., Storaska, D., Daniel, G., Hsu, L., Weinfurtner, O., Boehler, T., Schnell, J., Frankowsky, G., Netis, D., Ross, J., Reith, A., Kiehl, O., Wordeman, M.
Published in 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177) (2001)
Published in 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177) (2001)
Get full text
Conference Proceeding
A 390 mm/sup 2/ 16-bank 1 Gb DDR SDRAM with hybrid bitline architecture
Kirihata, T., Mueller, G., Ji, B., Frankowsky, G., Ross, J., Terletzki, H., Netis, D., Weinfurtner, O., Hanson, D., Daniel, G., Hsu, L., Storaska, D., Reith, A., Hug, M., Guay, K., Selz, M., Poechmueller, P., Hoenigschmid, H., Wordeman, M.
Published in 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278) (1999)
Published in 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278) (1999)
Get full text
Conference Proceeding